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openhwgroup
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corev-gcc
GNU General Public License v2.0
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toolchain installtion/usage issue
#112
chchenl
opened
2 days ago
0
XCVbitmanip: merge custom and standard builtins
#111
MaryBennett
opened
1 month ago
0
XCVsimd builtin optimisation enhancement
#110
zhixiao-zhang
opened
2 months ago
0
Modify xcvmem test cases to run for Os, Oz and Og
#109
zhixiao-zhang
closed
4 months ago
1
Post-inc: tests don't generate instructions for Og
#108
MaryBennett
opened
5 months ago
1
Update CORE-V documentation.
#107
jeremybennett
closed
5 months ago
1
CORE-V bitmanip builtin failure with bclr/bset
#106
jeremybennett
closed
6 months ago
2
CORE-V bitmanip extract failures with -O1
#105
jeremybennett
closed
6 months ago
1
Hardware Loops registers not saved/restored before being used in synchronous/asynchronous exception handler
#104
pascalgouedo
opened
7 months ago
2
Roll forward - 19th March 2024
#103
Slattz
closed
8 months ago
1
Rebase on non-broken upstream (building with newlib)
#102
simonpcook
closed
8 months ago
0
HW Loop produces an ICE during building
#101
Slattz
closed
8 months ago
2
Add header file for XCVsimd
#100
MaryBennett
closed
10 months ago
1
Add header file for XCVbitmanip
#99
MaryBennett
closed
10 months ago
1
Add header file for XCVmac
#98
MaryBennett
closed
10 months ago
1
Add header file for XCVelw
#97
MaryBennett
closed
10 months ago
1
Change xcvmem tests to run for Os and Oz
#96
MaryBennett
closed
10 months ago
1
Roll forward
#95
MaryBennett
closed
10 months ago
0
Add header file for XCValu
#94
MaryBennett
closed
10 months ago
1
Change the priority of the XCVmem instructions
#93
MaryBennett
closed
11 months ago
1
pseudo instruction "LA" not translating to correct instructions
#92
dd-vaibhavjain
closed
10 months ago
5
Tests added for XCVhwlp
#91
MaryBennett
closed
11 months ago
1
cannot find suitable multilib during the build, though it is shown in the toolchain lib folder.
#90
superflyers
closed
3 months ago
4
Add regression tests for hardware loop failures in issues #83 and #84
#89
MaryBennett
closed
10 months ago
1
xcvmem `mem (reg + reg)` instructions require corev.md to be above movSI.
#88
MaryBennett
closed
10 months ago
1
Roll forward
#87
MaryBennett
closed
12 months ago
0
.option norvc is ignored with Zca
#86
Wren6991
closed
11 months ago
2
Update README
#85
MaryBennett
closed
1 year ago
3
Hardware loops causes ICE in final_scan_insn_1
#84
jeremybennett
closed
11 months ago
5
Hardware loops causes relocation truncated to fit: R_RISCV_CVPCREL_UI12
#83
jeremybennett
closed
11 months ago
3
Exclude CORE-V memory tests for compressed code generation.
#82
jeremybennett
closed
1 year ago
1
Fix for Issue #77
#81
MaryBennett
closed
1 year ago
1
Jwr gcc14 xcvhwlp
#80
MaryBennett
closed
1 year ago
0
backport CORE-V HW loop.
#79
MaryBennett
closed
1 year ago
0
Hardware Loops march option not recognized
#78
pascalgouedo
closed
1 year ago
1
Incorrect code generation with PULP march with 20231017 release
#77
pascalgouedo
closed
1 year ago
1
Jwr gcc14 xcvhwlp
#76
MaryBennett
closed
1 year ago
0
Fix mem_plus_reg predicate
#75
MaryBennett
closed
1 year ago
2
[XCVmem] Normal register-immediate store not recognized
#74
MaryBennett
closed
1 year ago
3
illegal operands `flw fa5,t2(s1) is generated from the latest release toolchain (05/Sep)
#73
superflyers
closed
1 year ago
2
Fix cv.shuffle.b.sci immediate operand
#72
MaryBennett
closed
1 year ago
2
Fixes to xcvbitmanip and xcvsimd
#71
MaryBennett
closed
1 year ago
4
unrecognized opcode 'csrr' extension 'zicsr' required
#70
promodkumar-ashling
closed
1 year ago
6
WIP: Added a CORE-V builtins header file
#69
MaryBennett
closed
1 year ago
1
cv-simd-shufflei* incorrect builtin
#68
MaryBennett
closed
1 year ago
2
How to check COREV_CLUSTER for Event Load Instruction
#67
ChunyuLiao
closed
1 year ago
2
Prevent non-xcvmem post-inc load/stores
#66
MaryBennett
closed
1 year ago
2
Added __builtin_riscv_cv_simd_neg_[h,b]
#65
MaryBennett
closed
1 year ago
2
illegal operand error for "sw" operation
#64
superflyers
closed
1 year ago
2
Name change for post inc operands
#63
MaryBennett
closed
1 year ago
2
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