zchamski
commented
1 year ago Local CI tests confirm that Verilator v5 copes well with assertions: after removing the ifndef VERILATOR occurrences in core/*.sv model builds OK, simulations run w/o failure. Work in progress...
Is there an existing CVA6 bug for this?
Bug Description
Hello,
In CVA6 core, plenty of ifndef VERILATOR conditions RTL. Are asserts supported by new Verilator 5 version ? If it is the case, we could remove them from RTL.
core/include/instr_tracer_pkg.sv: ifndef VERILATOR core/include/ariane_pkg.sv: ifndef VERILATOR core/csr_regfile.sv: ifndef VERILATOR core/mmu_sv39/tlb.sv: ifndef VERILATOR core/mmu_sv32/cva6_tlb_sv32.sv: ifndef VERILATOR core/load_unit.sv: ifndef VERILATOR core/store_buffer.sv: ifndef VERILATOR core/issue_read_operands.sv: ifndef VERILATOR core/cache_subsystem/cva6_icache.sv: ifndef VERILATOR core/cache_subsystem/wt_dcache_missunit.sv: ifndef VERILATOR core/cache_subsystem/cache_ctrl.sv: ifndef VERILATOR core/cache_subsystem/wt_dcache_wbuffer.sv: ifndef VERILATOR core/cache_subsystem/wt_axi_adapter.sv: ifndef VERILATOR core/cache_subsystem/tag_cmp.sv: ifndef VERILATOR core/cache_subsystem/std_cache_subsystem.sv: ifndef VERILATOR core/cache_subsystem/wt_dcache_mem.sv: ifndef VERILATOR core/cache_subsystem/wt_l15_adapter.sv: ifndef VERILATOR core/cache_subsystem/wt_cache_subsystem.sv: ifndef VERILATOR core/cache_subsystem/miss_handler.sv: ifndef VERILATOR core/cache_subsystem/miss_handler.sv: ifndef VERILATOR core/cache_subsystem/wt_dcache.sv: ifndef VERILATOR core/cache_subsystem/wt_dcache_ctrl.sv: ifndef VERILATOR core/axi_shim.sv: ifndef VERILATOR core/scoreboard.sv: ifndef VERILATOR core/frontend/instr_queue.sv: ifndef VERILATOR core/frontend/frontend.sv: ifndef VERILATOR core/cva6.sv: ifndef VERILATOR core/cva6.sv: ifndef VERILATOR common/local/util/ex_trace_item.svh: ifndef VERILATOR common/local/util/instr_tracer_if.sv: ifndef VERILATOR common/local/util/instr_tracer.sv: ifndef VERILATOR common/local/util/instr_trace_item.svh: ifndef VERILATOR