Implement CBO in LSU and IFU

openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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Implement CBO in LSU and IFU #356

Closed davidharrishmc closed 10 months ago

davidharrishmc commented 1 year ago

IEU produces CMOpM, LSUPrefetchM that go to LSU Also produces IFUPrefetchE that should go to IFU During prefetch, IEU generates prefetch address on IEUAdrE

@ross144, it's ready for you to implement the CMO operations and prefetch. Suggest LSUPrefetchM be equivalent to a read (with rd = x0) IFUPrefetchM only prefetches if the cache is idle to avoid new stalls?

davidharrishmc commented 1 year ago

On further thought, prefetch should be ignored because cache line fetches are blocking so it doesn't help.

CMOOpM also needs to go to IFU.

ross144 commented 10 months ago

I've completed the CBOM and CBOZ extensions.

davidharrishmc commented 10 months ago

PR 393, PR 383, PR389. Done and verified by Ross.