Add support for new optional instruction format register attribute "RegIsDestination"

[jleidel]

This is a boolean value attributed to an instruction format's register field to set whether a register field is the target for a given operation. EG, Rt = Ra + Rb; Rt is the destination.

Sample yaml: `InstFormats:

• InstFormatName: TEST100.if ISA: TEST100.isa FormatWidth: 8 Fields:
  • FieldName: opcode FieldType: CGInstCode FieldWidth: 8 StartBit: 0 EndBit: 7 MandatoryField: true
  • FieldName: ra FieldType: CGInstReg FieldWidth: 5 StartBit: 0 EndBit: 4 MandatoryField: false RegClass: TEST100.regclass RegIsDestination: false`

[jleidel]

this feature is currently on the CoreGen devel branch; https://github.com/opensocsysarch/CoreGen/commit/c847039ddf03f40762d68e370c457cba79f46829

[jleidel]

fixed in 5fc27cf