Connect B0,B2. Did need to go down to 5mil traces (just short ones for the change, not globally) but kept the prior spacing. Well within JLCPCB specs for cheap 2 layer. (and conservative with respect to spacing)
Replaced the C16 footprint with an 8mm diameter one because I can't find any evidence that 16V+ 470uF caps exist in the footprint that was used (lcsc, digikey, mouser) and played a large amount of tetris to fit it (the 5mm will still fit if it exists). While there are a few 6.7's they are rare enough that it seems like asking for future supply chain disruption.
I suspect that B0 could be disconnected (which I did not do because I wasn't sure) in which case the 5mil traces would be unnecessary. It is very tight between the two MCUs.
Should note: this passes DRC and has been ordered but not built yet.
Connect B0,B2. Did need to go down to 5mil traces (just short ones for the change, not globally) but kept the prior spacing. Well within JLCPCB specs for cheap 2 layer. (and conservative with respect to spacing)
Replaced the C16 footprint with an 8mm diameter one because I can't find any evidence that 16V+ 470uF caps exist in the footprint that was used (lcsc, digikey, mouser) and played a large amount of tetris to fit it (the 5mm will still fit if it exists). While there are a few 6.7's they are rare enough that it seems like asking for future supply chain disruption.
I suspect that B0 could be disconnected (which I did not do because I wasn't sure) in which case the 5mil traces would be unnecessary. It is very tight between the two MCUs.
Should note: this passes DRC and has been ordered but not built yet.