Minibar FPGA Outline

[Aaron-Hartwig]

I'm trying to sketch out the work here before I go on leave. I think most of the work here will be plumbing into blocks we've already written, but there will be other little things that will need to be new (e.g. whatever sequencing is needed).

• Need hot swap control from 54V in to the Gimlet input.
• Need to handle the auxiliary PCIe signals from the Gimlet. At first, this can probably be pass-through to the PCIe connector, but it would be nice to expose a read interface here to let the SP get state. Perhaps we'd also want some control registers here at some point too.
  • We need to pass PRSNT# and PERST# through.
  • We need to monitor PCIe power supplies and generate PWRFLT# as appropriate (can probably just use PCIeEndpointController.bsv for various parts of this).
  • Can likely start with just passing through the SMBus signals, but we could develop other stuff here.
  • Generate PCIE_ALERT_L via an open drain buffer. Gimlet host software may not pay attention to this yet.
• SPI interface to the SP for register control
  • We currently hand roll these special per design, so it can heavily borrow from a *SpiServer.bsv of choice. The QSFP design's may be a good spot to start.
• We need to have two IgnitionControllers, one for each target to think its talking to its own Sidecar.

[isobering]

For hardware bringup, we only need a very simple FPGA image to turn Minibar on. Here are the things we want the FPGA to do for bringup:

• Successfully load the FPGA image from the SP's aux Flash over SPI. The ability to just load the image confirms that the SPI interface to the FPGA works and the rest of the FPGA image programming/loading chain (i.e., loading it into Aux Flash) works as well.
• Blink an LED to indicate that the image loaded successfully and that the design is running.
• Set static levels on select FPGA pins to turn on Minibar's power supply rails and other hardware features.

To accomplish these things, here's what the FPGA image needs to do:

• Blink the active-low status LED FPGA_STATUS_LED_EN_L
• Assert a high level on FPGA_TO_VSC7448_RESET_L
• Assert a high level on FPGA_TO_VSC8504_RESET_L_V3P3
• Assert a high level on FPGA_TO_V12_PCIE_EFUSE_EN
• Assert a high level on FPGA_TO_V3P3_PCIE_EFUSE_EN
• Assert a low level on FPGA_TO_PCIE_AUX_REFCLK_BUFFER_OE1_L
• Assert a high level on FPGA_TO_PCIE_AUX_REFCLK_BUFFER_OE0_L
• Assert a low level on FPGA_TO_PCIE_AUX_REFCLK_BUFFER_PD_L
• Assert a low level on FPGA_TO_PCIE_AUX_REFCLK_BUFFER_BW_SEL
• Assert a high level on FPGA_TO_VBUS_SYS_HSC_RESTART_L
• Assert a high level on FPGA_TO_VBUS_SLED_HSC_RESTART_L
• Assert a low level on FPGA_TO_VBUS_SLED_HSC_EN
• Assert a high level on FPGA_TO_POWER_LED_EN
• Tristate all other FPGA pins

The FPGA section of Minibar's Hardware Reference Manual has a table containing the mapping between signals and FPGA pins.