Unexpected behavior about CRPR

[SunAnICB]

When using PrimeTime to report crpr

...
                                                       0.01682 &  3.85848 r
  clock reconvergence pessimism                       -0.44692    3.41156
  clock uncertainty                                    0.15000    3.56156
  library removal time                                 0.22866    3.79023
  data required time                                              3.79023
  ------------------------------------------------------------------------------
  data required time                                              3.79023
  data arrival time                                              -4.17117
  ------------------------------------------------------------------------------
  slack (MET)                                                     0.38094

but using opensta

...
   0.150000    4.007700   clock uncertainty
   0.000000    4.007700   clock reconvergence pessimism
   0.228664    4.236365   library removal time
               4.236365   data required time
-----------------------------------------------------------------
               4.236365   data required time
              -4.178118   data arrival time
-----------------------------------------------------------------
              -0.058247   slack (VIOLATED)

which shows clock reconvergence pessimism is wrong. We tried debug this and found two tags mismatch. The root cause is the return value of tagStateEqualCrpr. The arrival time is same with pt. So we thought these two tags should match for CRPR.

Here is the debug log

(gdb) up
#1  0x000000000934693c in sta::tagMatchCrpr (tag1=0x53a1de00, tag2=0x53a1db60) at /home/project/peng/EEEE/openroad/src/sta/search/Tag.cc:528
528                && tagStateEqualCrpr(tag1, tag2));
(gdb) up    
#2  0x000000000949b016 in sta::CheckCrpr::otherMinMaxArrival (this=0xdcc02c0, path=0x7fffffffd6e0) at /home/project/peng/EEEE/openroad/src/sta/search/Crpr.cc:111
111            if (tagMatchCrpr(other->tag(this), tag))
(gdb) p other->tag(this)->asString(this)
$97 = 0x700f7000 "4014 ^ max/1main_clk_RTC ^ (clock prop) clk_src u_dig_top/u_mcu_clkctrl/clk_div_0/u_clkmux/u_clkmux_d0nt/Z PathDelay 15.625ns -max -from {CLK_RTC, DCLK_RTC, DCLK_RTC_DIV, HCLK_RTC, HCLK_RTC_DIV, PCLKG_RTC, PCLKG_RTC_DIV, PCLK_RTC, PCLK_RTC_DIV, SCLK_RTC, SCLK_RTC_DIV, clk1_RTC, clk_adc_RTC, clk_adc_RTC_DIV, clk_adc_div_RTC, clk_adc_div_RTC_DIV, clk_dac0_RTC, clk_dac0_RTC_DIV, clk_dac1_RTC, clk_dac1_RTC_DIV, clk_div0_clk_1_RTC_DIV} -to {clk2_XTAL, clk_div1_clk_1_XTAL_DIV, clk_div1_clk_g0_XTAL_DIV, clk_div1_clk_g1_XTAL, rtc_clk_XTAL, rtc_clk_XTAL_DIV} PathDelay 15.625ns -max -from {CLK_RTC, DCLK_RTC, DCLK_RTC_DIV, HCLK_RTC, HCLK_RTC_DIV, PCLKG_RTC, PCLKG_RTC_DIV, PCLK_RTC, PCLK_RTC_DIV, SCLK_RTC, SCLK_RTC_DIV, clk1_RTC, clk_adc_RTC, clk_adc_RTC_DIV, clk_adc_div_RTC, clk_adc_div_RTC_DIV, clk_dac0_RTC, clk_dac0_RTC_DIV, clk_dac1_RTC, clk_dac1_RTC_DIV, clk_div0_clk_1_RTC_DIV} -to {clk2_PLL, clk_div1_clk_1_PLL_DIV, clk_div1_clk_g0_PLL_DIV, clk_div1_clk_g1_PLL, rtc_clk_PLL, rtc_clk_PLL_DIV} PathDelay 15.625ns -max -from {CLK_RTC, DCLK_RTC, DCLK_RTC_DIV, HCLK_RTC, HCLK_RTC_DIV, PCLKG_RTC, PCLKG_RTC_DIV, PCLK_RTC, PCLK_RTC_DIV, SCLK_RTC, SCLK_RTC_DIV, clk1_RTC, clk2_RTC, clk_adc_RTC, clk_adc_RTC_DIV, clk_adc_div_RTC, clk_adc_div_RTC_DIV, clk_dac0_RTC, clk_dac0_RTC_DIV, clk_dac1_RTC, clk_dac1_RTC_DIV} -to {CLK_SWD} PathDelay 15.625ns -max -from {CLK_RTC, DCLK_RTC, DCLK_RTC_DIV, HCLK_RTC, HCLK_RTC_DIV, PCLKG_RTC, PCLKG_RTC_DIV, PCLK_RTC, PCLK_RTC_DIV, SCLK_RTC, SCLK_RTC_DIV, clk1_RTC, clk2_RTC, clk_adc_RTC, clk_adc_RTC_DIV, clk_adc_div_RTC, clk_adc_div_RTC_DIV, clk_dac0_RTC, clk_dac0_RTC_DIV, clk_dac1_RTC, clk_dac1_RTC_DIV} -to {CLK_XTAL, clk0_XTAL} PathDelay 15.625ns -max -from {CLK_RTC, DCLK_RTC, DCLK_RTC_DIV, HCLK_RTC, HCLK_RTC_DIV, PCLKG_RTC, PCLKG_RTC_DIV, PCLK_RTC, PCLK_RTC_DIV, SCLK_RTC, SCLK_RTC_DIV, clk1_RTC, clk2_RTC, clk_adc_RTC, clk_adc_RTC_DIV, clk_adc_div_RTC, clk_adc_div_RTC_DIV, clk_dac0_RTC, clk_dac0_RTC_DIV, clk_dac1_RTC, clk_dac1_RTC_DIV} -to {CLK_PLL, clk0_PLL, rch_PLL}"
(gdb) p tag->asString(this)
$98 = 0x70167600 "4012 ^ min/0main_clk_RTC ^ (clock prop) clk_src u_dig_top/u_mcu_clkctrl/clk_div_0/u_clkmux/u_clkmux_d0nt/Z False -min -from {CLK_RTC, DCLK_RTC, DCLK_RTC_DIV, HCLK_RTC, HCLK_RTC_DIV, PCLKG_RTC, PCLKG_RTC_DIV, PCLK_RTC, PCLK_RTC_DIV, SCLK_RTC, SCLK_RTC_DIV, clk1_RTC, clk_adc_RTC, clk_adc_RTC_DIV, clk_adc_div_RTC, clk_adc_div_RTC_DIV, clk_dac0_RTC, clk_dac0_RTC_DIV, clk_dac1_RTC, clk_dac1_RTC_DIV, clk_div0_clk_1_RTC_DIV} -to {clk2_PLL, clk2_XTAL, clk_div1_clk_1_PLL_DIV, clk_div1_clk_1_XTAL_DIV, clk_div1_clk_g0_PLL_DIV, clk_div1_clk_g0_XTAL_DIV, clk_div1_clk_g1_PLL, clk_div1_clk_g1_XTAL, rtc_clk_PLL, rtc_clk_PLL_DIV, rtc_clk_XTAL, rtc_clk_XTAL_DIV} False -min -from {CLK_RTC, DCLK_RTC, DCLK_RTC_DIV, HCLK_RTC, HCLK_RTC_DIV, PCLKG_RTC, PCLKG_RTC_DIV, PCLK_RTC, PCLK_RTC_DIV, SCLK_RTC, SCLK_RTC_DIV, clk1_RTC, clk2_RTC, clk_adc_RTC, clk_adc_RTC_DIV, clk_adc_div_RTC, clk_adc_div_RTC_DIV, clk_dac0_RTC, clk_dac0_RTC_DIV, clk_dac1_RTC, clk_dac1_RTC_DIV} -to {CLK_PLL, CLK_XTAL, clk0_PLL, clk0_XTAL, rch_PLL} False -min -from {CLK_PLL, CLK_RTC, CLK_XTAL, DCLK_PLL, DCLK_PLL_DIV, DCLK_RTC, DCLK_RTC_DIV, DCLK_XTAL, DCLK_XTAL_DIV, HCLK_PLL, HCLK_PLL_DIV, HCLK_RTC, HCLK_RTC_DIV, HCLK_XTAL, HCLK_XTAL_DIV, PCLKG_PLL, PCLKG_PLL_DIV, PCLKG_RTC, PCLKG_RTC_DIV, PCLKG_XTAL, PCLKG_XTAL_DIV} -to {CLK_SWD}"
(gdb) up     
#3  0x000000000949c3a1 in sta::CheckCrpr::crprArrivalDiff (this=0xdcc02c0, path=0x7fffffffd6e0) at /home/project/peng/EEEE/openroad/src/sta/search/Crpr.cc:330
330          Arrival other_arrival = otherMinMaxArrival(path);
(gdb) l
325        }
326        
327        float
328        CheckCrpr::crprArrivalDiff(const PathVertex *path)
329        {
330          Arrival other_arrival = otherMinMaxArrival(path);
331          float crpr_diff = abs(delayAsFloat(path->arrival(this))
332                                - delayAsFloat(other_arrival));
333          return crpr_diff;
334        }
(gdb) down
#2  0x000000000949b016 in sta::CheckCrpr::otherMinMaxArrival (this=0xdcc02c0, path=0x7fffffffd6e0) at /home/project/peng/EEEE/openroad/src/sta/search/Crpr.cc:111
111            if (tagMatchCrpr(other->tag(this), tag))
(gdb) l
106          VertexPathIterator other_iter(path->vertex(this),
107                                        path->transition(this),
108                                        other_ap, this);
109          while (other_iter.hasNext()) {
110            PathVertex *other = other_iter.next();
111            if (tagMatchCrpr(other->tag(this), tag))
112              return other->arrival(this);
113          }
114          // No corresponding path found.
115          // Match the arrival so the difference is zero.
(gdb) p other->arrival(this)
$99 = 3.20367555e-09
(gdb) l
116          return path->arrival(this);
117        }
118        
119        Crpr
120        CheckCrpr::checkCrpr(const Path *src_path,
121                             const PathVertex *tgt_clk_path)
122        {
123          Crpr crpr;
124          Pin *crpr_pin;
125          checkCrpr(src_path, tgt_clk_path, crpr, crpr_pin);
(gdb) p path->arrival(this)
$100 = 2.75808487e-09

[parallaxsw]

I can't help you without a testcase to look at the details of the paths.

[parallaxsw]

Based on the tags I am able to reproduce this in a small testcase.

[parallaxsw]

fixed by b8f2b078 issue107 crpr with clock min false and max delay exceptions