Stale timing results in presence of annotated slews

[povik]

Consider the following netlist

module top(a, y);
  input a;
  output y;
  wire w;
  sky130_fd_sc_hd__inv_1 a (
    .A(a),
    .Y(w)
  );
  sky130_fd_sc_hd__inv_1 b (
    .A(w),
    .Y(y)
  );
endmodule

and script

// https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/platforms/sky130hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_liberty sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog top.v
link_design top
report_checks -unconstrained -fields {slew}
sta::set_annotated_slew [[get_pin a/Y] vertices] [sta::cmd_corner] all rise_fall [expr 3.0 * 10.0**-9]
report_checks -unconstrained -fields {slew}

The second report reads

Startpoint: a (input port)
Endpoint: y (output port)
Path Group: unconstrained
Path Type: max

   Slew   Delay    Time   Description
----------------------------------------------------------------
           0.00    0.00 v input external delay
   0.00    0.00    0.00 v a (in)
   3.00    0.03    0.03 ^ a/Y (sky130_fd_sc_hd__inv_1)
   0.01    0.02    0.05 v b/Y (sky130_fd_sc_hd__inv_1)
   0.01    0.00    0.05 v y (out)
                   0.05   data arrival time
----------------------------------------------------------------
(Path is unconstrained)

but if you remove the first report_checks command, the report changes to

Startpoint: a (input port)
Endpoint: y (output port)
Path Group: unconstrained
Path Type: max

   Slew   Delay    Time   Description
----------------------------------------------------------------
           0.00    0.00 ^ input external delay
   0.00    0.00    0.00 ^ a (in)
   3.00    0.02    0.02 v a/Y (sky130_fd_sc_hd__inv_1)
   0.23    0.27    0.29 ^ b/Y (sky130_fd_sc_hd__inv_1)
   0.23    0.00    0.29 ^ y (out)
                   0.29   data arrival time
----------------------------------------------------------------
(Path is unconstrained)

The slew on the b/Y pin is different, which suggests results aren't properly invalidated when the annotated slew is set.

[parallaxsw]

Fixed in e5e33ccb issue33 set_assigned_transition output_pin incr dcalc BTW, the set_assigned_transition command is the official way to set a slew/transition.

[povik]

Thanks!

BTW, the set_assigned_transition command is the official way to set a slew/transition

Yes, what happened is I encountered this issue using the C++ API, and writing a Tcl reproducer the internal function was the first thing I found.

[parallaxsw]

Got it. I would still question setting the slew on the output of a gate since it does not change the delays of the gate or wires, just downstream of the gate.

[povik]

This is for a timing-driven buffering algorithm. We start with no buffering, so on high-fanout nets we have unreasonably high slews influencing the gates downstream of the net. With an annotation we can override it so that the required times on the input pins connected to the high-fanout net are a better estimate.