How to support latch with both postive and negative level-sensitive

[eaglechip]

20240705.zip

P.S.: The attachment file '20240705.zip' includes all the test case, run.tcl, and example pictures, which can be used directly to reproduce the issue.

Here is the issue description:

1. There is a latch cell that can operate in both positive and negative level-sensitive modes. And there is a pin to be configured whether its clock is inverted.
2. In the netlist, the latch cell can be instantiated with the clock inversion configuration pin connected to VCC for some instances and GND for other instances. We created a simple case for testing. Please see the latch_invert.v and picture1_netlist example.jpg in the attachment.
3. In order to support both situations, we have to describe both postive and negative scenarios in one cell in the liberty file. We tried to use the 'when' syntax to isolate them in one cell definition in liberty file, but got the incorrect result in the timing report, and the OpenSta reported some warnings when reading the liberty file. (see the cell "LATCH_TEST" definition in latch_invert.lib, and warnings in result.txt, both in the attachment.)

Could you please tell us how to describe this cell in the library? For example, should we describe the cell as two cells, such as cell (LATCH_TEST_rising) and cell (LATCH_TEST_falling) ? Or, is there any other effective way to handle this problem?

Thank you very much!

[jjcherry56]

fixed by 3ba6f0e5 issue44 liberty pos/neg latches