Parastics annotation issue

[kareefardi]

Hello. There seems to be a potential problem with net annotation with hierarchical designs. Here is a simple test case of two single cell macros that have long nets inside themselves and in between at the top level.test-case.tar.gz (Run sta.bash to reproduce).

Previously the report would look like this:

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.00    0.00    0.00   clock __VIRTUAL_CLK__ (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          2.00    2.00 ^ input external delay
     1    0.41    1.83    1.59    3.59 ^ in (in)
                                         in (net)
                  2.19    0.00    3.59 ^ inv_1/inv1/A (sky130_fd_sc_hd__inv_2)
     1    0.14    0.69    0.87    4.46 v inv_1/inv1/Y (sky130_fd_sc_hd__inv_2)
                                         inv_1/wire1 (net)
                  0.70    0.06    4.52 v inv_1/inv2/A (sky130_fd_sc_hd__inv_2)
     1    1.15    4.01    2.12    6.64 ^ inv_1/inv2/Y (sky130_fd_sc_hd__inv_2)
                                         glue (net)
                  9.33    4.46   11.10 ^ inv_2/inv1/A (sky130_fd_sc_hd__inv_2)
     1    0.14    2.15    2.67   13.77 v inv_2/inv1/Y (sky130_fd_sc_hd__inv_2)
                                         inv_2/wire1 (net)
                  2.16    0.06   13.83 v inv_2/inv2/A (sky130_fd_sc_hd__inv_2)
     1    0.46    2.04    2.28   16.11 ^ inv_2/inv2/Y (sky130_fd_sc_hd__inv_2)
                                         out (net)
                  2.29    0.57   16.68 ^ out (out)
                                 16.68   data arrival time

                  0.00   10.00   10.00   clock __VIRTUAL_CLK__ (rise edge)
                          0.00   10.00   clock network delay (ideal)
                         -0.25    9.75   clock uncertainty
                          0.00    9.75   clock reconvergence pessimism
                         -2.00    7.75   output external delay
                                  7.75   data required time
-----------------------------------------------------------------------------
                                  7.75   data required time
                                -16.68   data arrival time
-----------------------------------------------------------------------------
                                 -8.93   slack (VIOLATED)

Today this is the path reported:

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.00    0.00    0.00   clock __VIRTUAL_CLK__ (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          2.00    2.00 v input external delay
     1    0.11    0.26    0.22    2.22 v in (in)
                                         in (net)
                  0.29    0.00    2.22 v inv_1/inv1/A (sky130_fd_sc_hd__inv_2)
     1    0.14    0.63    0.58    2.81 ^ inv_1/inv1/Y (sky130_fd_sc_hd__inv_2)
                                         inv_1/wire1 (net)
                  0.64    0.06    2.86 ^ inv_1/inv2/A (sky130_fd_sc_hd__inv_2)
     1    0.00    0.09    0.06    2.93 v inv_1/inv2/Y (sky130_fd_sc_hd__inv_2)
                                         glue (net)
                  0.09    0.00    2.93 v inv_2/inv1/A (sky130_fd_sc_hd__inv_2)
     1    0.14    0.64    0.49    3.42 ^ inv_2/inv1/Y (sky130_fd_sc_hd__inv_2)
                                         inv_2/wire1 (net)
                  0.64    0.06    3.48 ^ inv_2/inv2/A (sky130_fd_sc_hd__inv_2)
     1    0.03    0.19    0.23    3.70 v inv_2/inv2/Y (sky130_fd_sc_hd__inv_2)
                                         out (net)
                  0.19    0.00    3.70 v out (out)
                                  3.70   data arrival time

                  0.00   10.00   10.00   clock __VIRTUAL_CLK__ (rise edge)
                          0.00   10.00   clock network delay (ideal)
                         -0.25    9.75   clock uncertainty
                          0.00    9.75   clock reconvergence pessimism
                         -2.00    7.75   output external delay
                                  7.75   data required time
-----------------------------------------------------------------------------
                                  7.75   data required time
                                 -3.70   data arrival time
-----------------------------------------------------------------------------
                                  4.05   slack (MET)

It looks like the top level nets are missing no properly annotated (e.g. glue net). The change in behavior happened with this commit 902a1bff86e0f725f47e49457dc260773fa418b6

[jjcherry56]

Thanks for the detailed testcase. Fixed in 3fb703b4 issue82 hierarchical spef annotation