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parallaxsw
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OpenSTA
GNU General Public License v3.0
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Long runtimes when reading SDCs that include a lot of `get_pins -hier`
#78
gadfort
closed
3 months ago
2
Add STA compatibility flags for object properties
#77
akashlevy
closed
3 months ago
0
Sdc.tcl: invoke original_source if we can
#76
oharboe
closed
3 months ago
5
Update `Dockerfile.ubuntu_18.04` and remove `filesystem` dependence completely in `Main.cc`
#75
akashlevy
closed
3 months ago
0
`cmake` fails when optional `tclreadline` library is missing
#74
akashlevy
closed
3 months ago
4
How should I check the CEFF of CCS?
#73
icesdu
closed
2 weeks ago
4
Add property-based filtering (`-filter` keyword arg) on all SDC `get_*` commands (+ DRY refactor)
#72
akashlevy
closed
3 months ago
3
Memory leak in `report_power`
#71
akashlevy
closed
3 months ago
3
Segfault when reading in Liberty file with missing `related_pin` in timing group
#70
akashlevy
closed
3 months ago
5
search: allow path groups updating to be triggered externally
#69
AcKoucher
closed
3 months ago
2
CentOS/RHEL 7 Dockerfile
#67
akashlevy
closed
3 months ago
5
ClockTree Arrival time issue
#66
wuheng01
closed
3 months ago
6
Why Ceff is 0?
#65
icesdu
closed
3 months ago
2
Create partial set of one-to-one timing arcs for Liberty cell buses when input/output widths are mismatched
#64
akashlevy
closed
3 months ago
1
`proc_redirect report_disabled_edges`
#63
akashlevy
closed
3 months ago
0
Add static qualifier to StaTclTypes.i helpers
#62
povik
closed
3 months ago
1
Fix clang warnings about wrong abs
#61
maliberty
closed
3 months ago
1
Refactor `filter_*` and add support for `!~`
#60
akashlevy
closed
3 months ago
0
Refactor using C++ templates?
#59
akashlevy
closed
3 months ago
2
Support `!~` in filter expressions
#58
akashlevy
closed
3 months ago
0
Thread safety issue
#57
maliberty
closed
2 weeks ago
1
Update CmdUtil.tcl to add `sta::write_units_json`
#56
akashlevy
closed
4 months ago
0
typo in opensta.pdf
#55
Ravenslofty
closed
3 months ago
2
Make `info script` return path to script executing
#54
maliberty
opened
4 months ago
0
Add tcl get methods for power information
#53
maliberty
closed
3 months ago
2
Vast delays (resulting from infinity values) with stuck-low flipflops and split unateness in liberty timing
#52
gatecat
closed
4 months ago
1
sta segfault with broken power.tcl script
#51
maliberty
closed
3 months ago
1
Support JSON format and redirect to file for `report_units`
#50
akashlevy
closed
4 months ago
4
read_power_activities doesn't check for a linked network
#49
maliberty
closed
3 months ago
1
sta::write_liberty crash
#48
maliberty
closed
3 months ago
2
test_cell is not capturing sequential statements
#47
maliberty
closed
2 weeks ago
18
Update Property.cc to support more property types in filter expressions
#46
akashlevy
closed
4 months ago
4
corner creation notification?
#45
maliberty
closed
4 months ago
1
How to support latch with both postive and negative level-sensitive
#44
eaglechip
closed
4 months ago
1
Add is_pad attribute for LibertyPort
#43
wuheng01
closed
4 months ago
0
Genclks can't exit BfsBkwdIterator
#41
eaglechip
closed
5 months ago
1
Crash while reading Liberty with CCS
#40
maliberty
closed
5 months ago
1
power tests fail
#39
maliberty
closed
5 months ago
1
core dumped in ccs_sime1.tcl
#38
icesdu
closed
5 months ago
1
get_pins with -hier unable to find pins on wide busses
#37
gadfort
closed
5 months ago
1
get_pins segfaults with non-string property as filter
#36
gadfort
closed
5 months ago
1
Guarded insertion into filtered_arrivals_ in sta::Search
#35
jbylicki
closed
5 months ago
3
incorrect area reported with get_property
#34
gadfort
closed
5 months ago
2
Stale timing results in presence of annotated slews
#33
povik
closed
5 months ago
4
Write verilog doesn't write declaration for power net.
#32
smunaut
closed
5 months ago
16
How to use the gateDelay API without a specific Pin in CCS?
#31
maliberty
closed
6 months ago
1
synchronizing the arc delay calc
#30
maliberty
closed
6 months ago
1
Truncated help outputs
#29
nmoroze
closed
6 months ago
1
define_corners without load crashes
#28
maliberty
closed
6 months ago
4
Write verilog doesn't reflect interconnected power ports
#27
smunaut
closed
7 months ago
2
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