perlindgren / hippomenes

In love with Atalanta
10 stars 4 forks source link

Scheduling analysis #24

Open perlindgren opened 5 months ago

perlindgren commented 5 months ago

Background:

Hippomenes and the RISC-V RT (Real Time extention) specification have the aim to provide an outset for implementing systems with (hard) real-time constraints. As such all operations are bound time/cycles. For the current specification all instructions (including memory and peripheral accesses) are single-cycle and latency free. This is accomplished by careful memory system design and CSR mapped peripherals. Altogether, the design of Hippomenes/RISC-V RT is thus amenable to static (as well as run-time) analysis and verification.

The RTIC framework allows the user to specify the application in terms of tasks, and resources (a common concept used in context of hard real-time systems). The recent/experimental implementation of RTIC takes a modular approach allowing customization in terms of third party compilation passes.

Problem:

Providing static scheduling analysis for RTIC applications running on the Hippomenes/RISC-V RT.

Solution:

The solution will be based on the integration of a set of external third party tools (not directly part of RISC-V RT). Tentatively, we can foresee a separation of concerns as follows:

Evaluation:

Real-Time Monitoring and Trace (RTMT) allows us to monitor events during execution. This functionality can be used to validate that observed and computed values complies.

We can use this issue to track the progress of scheduling analysis onto the Hippomenes/RISC-V RT target.