As part of the validation process, all CSR registers should be tested, ensuring that the hardware design is correct, and that corresponding SW abstractions are in correspondence to the underlying hardware.
However, writing (and even reading) CSRs may introduce side effects, e.g., triggering an interrupt or similarly. This is not an acute problem with the current Hippomenes implementation, as the number of CSRs is limited and hand written tests can circumvent most/all undesired side effects. However with extensibility in mind a test mode could be thought of, where peripherals (and internal CSRs) disable side effects with disrupting behavior. This would allow e.g., to check read/write correctness e.g., of interrupt pend bit.
As part of the validation process, all CSR registers should be tested, ensuring that the hardware design is correct, and that corresponding SW abstractions are in correspondence to the underlying hardware.
However, writing (and even reading) CSRs may introduce side effects, e.g., triggering an interrupt or similarly. This is not an acute problem with the current Hippomenes implementation, as the number of CSRs is limited and hand written tests can circumvent most/all undesired side effects. However with extensibility in mind a test mode could be thought of, where peripherals (and internal CSRs) disable side effects with disrupting behavior. This would allow e.g., to check read/write correctness e.g., of interrupt pend bit.