Extending the number of Vector Registers

[HakamAtassi]

Hello @pphilippos ,

Hope you are well.

I've been working on an algorithm that very specificly requires 10 vector registers instead of the 4 that is currently supported. Based one the code, I was able to find a parameter that seems to control the number of VREGS provided, but when I increase it to 8, I'm able to perform a c0_lv instruction, but the c0_sv instruction does not even compile. I suspect that this is a result of the opcode encoding or something to that extent.

The first step is to figure out how to increase the number of vectors from 4-> 8 using the parameter provided.

The second step is to increase the number of registers for 8->10 by messing with the RTL and potentially the opcodes/opcode masks, if needed.

I'll provide some screenshots from my other laptop in just a second.

If you could help me figure this out, that would be great. Thanks.

[HakamAtassi]

Above indicates that loads and stores to/from vector 4 works fine.

Some opcode error pops up when I try to store from vector 8.

Here are the masks for the instructions. They are unchanged from the documentation you provided. I've experimented with them slightly in trying to debug this issue, but changing the mask to 0xf07f did not seem to help (although this is worth trying again, could have been a build issue of sorts).

Hope this helps.

[pphilippos]

Thank you for using the softcore, (and for the recent pull request, but was too busy to monitor all the changes..) 4 vector registers was a hard limitation, but originally still sufficient for our research purposes. There are a few places that need to be modified to add more than 4 (mask from the SW side, but also internally) (don't remember how easy, I think it's easy). Will try to find time to check this out.

[HakamAtassi]

No worries, I greatly appreciate your prompt responses none the less. As for the previous pull request, you can just discard it to be frank. I never reviewed my changes and noticed I modified too many files unnccesarily- its quite a messy pull.

Regardless, let me know what you find. Any help would be grealy appreciated. Take care.

[pphilippos]

Hello, can you try replacing

            for (i=0; i<4; i=i+1) begin
                reg_file_v[i]<=0;  reg_pend_v[i]<=0;                

with

            for (i=0; i<`NumVregisters; i=i+1) begin
                reg_file_v[i]<=0;  reg_pend_v[i]<=0;        

in cpu.v? (for NumVregisters=8) There might be other places, but this is an easy one I think.

[HakamAtassi]

Hey,

Did you do any modifications to the instruction mask? At the moment my compiler is erroring out likely due to 7<<9 exceeding the number of bits checked by the mask.

[pphilippos]

Hello, I haven't had the chance to check the software support part yet. Other than checking the RISC-V manual, maybe the GCC code needs some more editing as the vector instructions here do not follow the standard format completely. I will check it out at some point and let you know. In the worst case you may also edit the binaries by hand, if you are in a hurry. Thanks - Philippos