search

pulp-platform / pulpino

An open-source microcontroller system based on RISC-V
http://www.pulp-platform.org
Other
899 stars 298 forks source link

!!!Possibly Wrong AXI Signals!!! #361

Open ghost opened 4 years ago

ghost commented 4 years ago

Screenshot from 2020-10-07 16-29-09 Although write_data is valid, writte_valid signal is coming with a 1 cycle latency to the AXI master port. Is'nt it an AXI protocol error?! Please check it.

barrydebruin commented 4 years ago

There are no latency constraints in the AXI standard. The wvalid signal can come whenever it wants after awvalid has been issued. You can rely on the data being valid when wvalid is high. If wvalid is low anything may happen, its not defined.