How to program multiple cores using openocd

[rtspk]

Hi Guys,

I am in the process of implementing a multicore version of the pulpissimo.

• I have four RISCY cores.
• They all share the same L2 memory.
• The regions of the L2 memory are different for each core. (i.e., the code memory of each core starts with a certain offset)

Currently, I am stuck on the openocd part. How do you program multiple cores using openocd?

I am use the following steps to program the cores.

Starting JTAG

openocd -f olimex_arty.cfg This statement sets up the Jtag connection.

Open On-Chip Debugger 0.12.0+dev-03815-gfdd07f127 (2024-06-19-14:31)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter speed' not 'adapter_khz'
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'ftdi device_desc' not 'ftdi_device_desc'
DEPRECATED! use 'ftdi vid_pid' not 'ftdi_vid_pid'
DEPRECATED! use 'ftdi layout_init' not 'ftdi_layout_init'
DEPRECATED! use 'ftdi layout_signal' not 'ftdi_layout_signal'
DEPRECATED! use 'ftdi layout_signal' not 'ftdi_layout_signal'
DEPRECATED! use 'ftdi layout_signal' not 'ftdi_layout_signal'
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.unknown0 tap/device found: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Warn : JTAG tap: riscv.unknown0       UNEXPECTED: 0x10102001 (mfg: 0x000 (<invalid>), part: 0x0102, ver: 0x1)
Error: JTAG tap: riscv.unknown0  expected 1 of 1: 0x5fffedb3 (mfg: 0x6d9 (PULP Platform), part: 0xfffe, ver: 0x5)
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Warn : JTAG tap: riscv.cpu       UNEXPECTED: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Error: JTAG tap: riscv.cpu  expected 1 of 1: 0x50001db3 (mfg: 0x6d9 (PULP Platform), part: 0x0001, ver: 0x5)
Error: Trying to use configured scan chain anyway...
Warn : Bypassing JTAG setup events due to errors
Info : [riscv.cpu] datacount=2 progbufsize=8
Info : [riscv.cpu] Vector support with vlenb=0
Info : [riscv.cpu] S?aia detected with IMSIC
Info : [riscv.cpu] Examined RISC-V core
Info : [riscv.cpu]  XLEN=32, misa=0x40901104
[riscv.cpu] Target successfully examined.
Info : [riscv.cpu] Examination succeed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
riscv.cpu halted due to debug-request.
Ready for Remote Connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333
riscv.cpu halted due to debug-request.
Warn : Prefer GDB command "target extended-remote :3333" instead of "target remote :3333"
Info : dropped 'gdb' connection
Info : accepting 'gdb' connection on tcp/3333

Starting GDB

[abcd@efgh123 dhrystone]$ riscv32-unknown-elf-gdb core0
GNU gdb (GDB) 7.12.50.20170505-git
Copyright (C) 2016 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv32-unknown-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from core0...done.
(gdb) tareget remote localhost:3333
Undefined command: "tareget".  Try "help".
(gdb) target remote localhost:3333
Remote debugging using localhost:3333
warning: Target-supplied registers are not supported by the current architecture
_start () at /home/syed/tetrisc_v2/pulp-runtime/kernel/crt0.S:137
137     jal x0, pos_init_entry
(gdb) load

**### Here i programmed the core 0** 

Loading section .init_array, size 0xc lma 0x1c000004
Loading section .fini_array, size 0xc lma 0x1c000010
Loading section .rodata, size 0xfc lma 0x1c00001c
Loading section .data, size 0x28 lma 0x1c000920
Loading section .vectors, size 0xc0 lma 0x1c004000
Loading section .text, size 0x1e60 lma 0x1c0040c0
Start address 0x1c004080, load size 8284
Transfer rate: 449 KB/sec, 1380 bytes/write.
(gdb) load core1
**### Here i programmed the core 1** 
Loading section .init_array, size 0xc lma 0x1c010004
Loading section .fini_array, size 0xc lma 0x1c010010
Loading section .rodata, size 0x68 lma 0x1c01001c
Loading section .vectors, size 0xc0 lma 0x1c014000
Loading section .text, size 0x1648 lma 0x1c0140c0
Start address 0x1c014080, load size 6024
Transfer rate: 392 KB/sec, 1204 bytes/write.
(gdb) load core2

**### Here i programmed the core 2** 

Loading section .init_array, size 0xc lma 0x1c020004
Loading section .fini_array, size 0xc lma 0x1c020010
Loading section .vectors, size 0xc0 lma 0x1c024000
Loading section .text, size 0x270 lma 0x1c0240c0
Start address 0x1c024080, load size 840
Transfer rate: 91 KB/sec, 210 bytes/write.
(gdb) load core3

**### Here i programmed the core 3** 

Loading section .init_array, size 0xc lma 0x1c030004
Loading section .fini_array, size 0xc lma 0x1c030010
Loading section .rodata, size 0x3c lma 0x1c03001c
Loading section .vectors, size 0xc0 lma 0x1c034000
Loading section .text, size 0x1630 lma 0x1c0340c0
Start address 0x1c034080, load size 5956
Transfer rate: 387 KB/sec, 1191 bytes/write.
(gdb) c
Continuing.
^C
Program received signal SIGINT, Interrupt.
0x1c03415c in ?? ()
(gdb) 

I see the output at the terminal. but i only the see the output of the core which i last programmed. in this case, core 3 as i programmed it last. so my question is, how can i run all the cores simultaneously ? Could you guys please narrow the problem for me.

Thanks alot.