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rahulk29
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sram22
A configurable SRAM generator
BSD 3-Clause "New" or "Revised" License
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Optimize control logic v2
#439
rahulk29
closed
1 year ago
0
Run PEX on SRAMs in sram22::main
#438
rahulk29
closed
1 year ago
0
Generate delay line abstract view (LEF)
#437
rahulk29
closed
1 year ago
0
Run PEX on the delay line
#436
rahulk29
closed
1 year ago
0
Run PEX on the TDCs
#435
rahulk29
closed
1 year ago
0
Test Chip Doc Updates
#434
rohanku
closed
1 year ago
0
Add TDC verilog model and abstract generation code
#433
rahulk29
closed
1 year ago
0
Update docs for SRAM control signals
#432
rahulk29
closed
1 year ago
0
SRAM test ports
#431
rohanku
closed
1 year ago
0
Generate LEF/LIB for Rocket SRAM macros
#430
rahulk29
closed
1 year ago
0
Fine TDC cell layout
#429
rahulk29
closed
1 year ago
0
Tunable Delay Line
#428
rohanku
closed
1 year ago
0
Fine TDC first pass layout
#427
rahulk29
closed
1 year ago
0
Allow non-power-of-two SRAM sizes
#426
rahulk29
opened
1 year ago
0
Change X to RAND in `test_chip.md`
#425
rahulk29
closed
1 year ago
0
Top Level LVS
#424
rohanku
closed
1 year ago
0
Shared BIST across all SRAM test macros
#423
rahulk29
closed
1 year ago
0
SRAM timing analysis chip documentation
#422
rahulk29
closed
1 year ago
0
Optimize control logic
#421
rahulk29
closed
1 year ago
0
Basic BIST RTL (Incomplete)
#420
rohanku
closed
1 year ago
0
Add coarse TDC schematic and testbench
#419
rahulk29
closed
1 year ago
0
BIST RTL
#418
rohanku
closed
1 year ago
0
Run formatter
#417
rahulk29
closed
1 year ago
0
Time-to-digital converter schematic
#416
rahulk29
closed
1 year ago
0
Update psfparser
#415
rahulk29
closed
1 year ago
0
psf-ascii changed to psfparser
#414
zzdywc
closed
1 year ago
3
Top Level LVS
#413
rohanku
closed
1 year ago
0
Control Logic LVS
#412
rohanku
closed
1 year ago
0
Tune control logic edge detector sizing
#411
rahulk29
closed
1 year ago
0
Allow CI to run on pull requests
#410
rohanku
closed
1 year ago
0
Github CI
#409
rohanku
closed
1 year ago
0
Deactivate CI temporarily
#408
rohanku
closed
1 year ago
0
Finish DRC and LVS for control logic
#407
rohanku
closed
1 year ago
0
Fix SR Latch Schematic
#406
rohanku
closed
1 year ago
0
Control Logic Replica V2 Layout
#405
rohanku
closed
1 year ago
0
Built-in self test RTL
#404
rahulk29
closed
1 year ago
0
Add control logic schematic generator
#403
rohanku
closed
1 year ago
0
Fix decoder jogs
#402
rohanku
closed
1 year ago
0
Expose SRAM Pins
#401
rohanku
closed
1 year ago
0
Col peripheral port
#400
rohanku
closed
1 year ago
0
Connect Bitcells to WL and BL Drivers
#399
rohanku
closed
1 year ago
0
Revert "Fix SRAM errors"
#398
rohanku
closed
1 year ago
0
Revert master
#397
rohanku
closed
1 year ago
0
Fix SRAM errors
#396
rohanku
closed
1 year ago
0
Fix Decoder Ports
#395
rohanku
closed
1 year ago
0
Power Strap Connections
#394
rohanku
closed
1 year ago
0
Port to subgeom
#393
rohanku
closed
1 year ago
0
LUT-based Liberty file generation
#392
rahulk29
opened
1 year ago
0
Detailed Routing
#391
rohanku
closed
1 year ago
0
Enable configurable Calibre PEX level
#390
rahulk29
closed
1 year ago
0
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