rems-project / sail-arm

Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
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Assertion fails on "stp/ldp q0, q1, [x0]" #8

Open dc-mak opened 4 years ago

dc-mak commented 4 years ago

opcode ad{0,4}00400

function memory_pair_simdfp_offset_memory_pair_simdfp_postidx__decode (Rt, Rn, Rt2, imm7, L, V, opc) = {                                                                                                          
    ...                                                                                                                                                                                                      
    let 'scale = 2 + UInt(opc);                                                                                                                                                                                   
    let 'datasize = shl_int(8, scale);                                                                                                                                                                            
    assert(constraint('datasize in {8, 16, 32, 64}));                                                                                                                                                             
    ...                                                                                                                  
}

and similarly for memory_pair_simdfp_preidx_memory_pair_simdfp_postidx__decode but for opcode ad{8,c}f7c1e "stp/ldp q30, q31, [x0, #480]!"

Also, shouldn't 'datasize be in 32 and 64 only because UInt(opc) is either 0 or 1?

Alasdair commented 4 years ago

The constraints are added automatically it doesn't understand anything intricate about shifts and the range of opc, it just knows what is required as a precondition for memory_pair_simdfp_postidx

That said I think maybe opc can be two allowing a 128 bit load.

Alasdair commented 4 years ago

Should be fixed now I think

Alasdair commented 4 years ago

I should add that we will likely need to ensure that the CPTR_EL2, CPACR, and HCR_EL2 registers are set appropriately to allow advanced simd instructions in EL2.