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riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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DVM #436

Closed yanhe234 closed 1 month ago

yanhe234 commented 1 month ago

Under the ARM architecture, SMMU supports DVM operations for failed PTE operations in addition to commands. Currently, there is no definition similar to DVM under the RV architecture. What is the reason for this? Looking forward to your answer

ved-rivos commented 1 month ago

The RISC-V ISA, similar to ISA such as x86, does not have an instruction equivalent to TLBI to do a DVM broadcast/multicast. If/when such an instruction gets defined then the IOMMU would also be a listener for such DVM like messages.

yanhe234 commented 1 month ago

Hello,sir. I understand that if we support something like DVM, would it have a significant impact on the entire ecosystem? And do you think this performance improvement is necessary?

ved-rivos commented 1 month ago

Whether it is a performance improvement compared to batched/deferred TLB invalidations using IPIs is uncertain. DVM type mechanism has however causes significant scaling and performance interference in even moderately large systems. For some background on this topic see: https://lore.kernel.org/lkml/20230518065934.12877-1-yangyicong@huawei.com/ https://lore.kernel.org/all/20230717131004.12662-5-yangyicong@huawei.com/T/#u https://www.youtube.com/watch?v=jyohnitbXSk Please do share any data/studies you have done in this space.