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riscv-non-isa / riscv-semihosting

https://lf-riscv.atlassian.net/browse/RVS-2673
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Clarification needed on definition of semihosting traps #10

Closed Silabs-ArjanB closed 4 months ago

Silabs-ArjanB commented 7 months ago

Section "2.3 Semihosting Execution Environment" refers to the RISC-V external debug specification as follows:

Of particular interest is the RISC-V external debug specification, which allows M-mode (and optionally S/U modes) ebreak instructions to be treated as semihosting traps.

The RISC-V external debug specification however does not mention the word semihosting at all. Can some explanation be added here using actual terminology from the RISC-V external debug specification about what it means to be 'treated as semihosting traps'?

avpatel commented 5 months ago

The section 2.3 has stale text and should be removed. I will update and create a 0.4 release tag.