riscv-non-isa / riscv-trace-spec

RISC-V Processor Trace Specification
https://jira.riscv.org/browse/RVG-88
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ldata/sdata for atomic and CSR data tracing #166

Open jaydipdmehta opened 1 month ago

jaydipdmehta commented 1 month ago

Etrace spec has below text:

Atomic and CSR accesses have either both load and store data, or store data and an operand. For CSRs and unified atomics, both values are reported via data, with the store data in the LSBs and the load data or operand in the MSBs

Its unclear what is carried on 'ldata' and 'sdata' of data trace interface for split load signalling, as above text mentions about LSBs and MSBs which seems to be valid for unified signalling? Can such information be detailed?

Meanwhile, can you clarify if below sentences are true for split signalling?

Thanks, Jaydip