Fix typo in debug integration spec

riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

https://jira.riscv.org/browse/RVG-148

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Fix typo in debug integration spec #378

Closed andresag01 closed 2 months ago

andresag01 commented 2 months ago

Fix reference to variable that was not previously define.
Change use of extension name variable to CHERI mode variable.