riscv / riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
https://jira.riscv.org/browse/RVG-148
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Swap roles of xtval and xtval2 #379

Closed andresag01 closed 2 months ago

andresag01 commented 2 months ago

Swap the roles of xtval and xtval2 such that xtval holds the address on a CHERI fault and xtval2 holds the extra CHERI cause and type information for the exception. The following also had to change along the way:

This PR is a follow up to https://github.com/riscv/riscv-cheri/pull/373

andresag01 commented 2 months ago

I do wonder if we want to allocate more values in cause instead of adding all the tval2 registers or if that is a more contentious change.

We considered this before, but didn't take that approach because it would consume too much space in *cause, and other places connected to it like medeleg. In future, we will probably need to remove the CHERI fault cause 28 and instead use the new software-check fault cause (see https://github.com/riscv/riscv-cheri/issues/60).

IMHO, we should keep what we currently have in the spec (and this PR) and await feedback from the ARC.

tariqkurd-repo commented 2 months ago

I do wonder if we want to allocate more values in cause instead of adding all the tval2 registers or if that is a more contentious change.

We considered this before, but didn't take that approach because it would consume too much space in *cause, and other places connected to it like medeleg. In future, we will probably need to remove the CHERI fault cause 28 and instead use the new software-check fault cause (see #60).

IMHO, we should keep what we currently have in the spec (and this PR) and await feedback from the ARC.

I agree with @andresag01 , I think it's better to keep what we have and all this area is subject to change by the ARC