This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
§3.13 makes repeated reference to capabilities "hav[ing] infinte bounds (see Section 2.1)", but the very short §2.1 does not define the term. Instead, that definition appears in §2.2.6, amidst the discussion of bounds encoding used in the draft.
And indeed, §2.2.6 itself seems a bit confused, referring the reader back to §2.1 for bounds decoding before launching into the details of bounds decoding. I suspect some historical editorial violence to the prose. ;)
I could suggest that there be a section introduced before §2.1 that gave a brief, abstract description of the components of capabilities, sort of like what the CHERI ISA documents have done, but that sounds like a fair bit of work for which I'm not champing at the bit to volunteer. As a simpler, hopefully sufficient, edit, could we just move the definition of "has infinite bounds" nearer the top of §2.2.6 and drop its erroneous xref to §2.1?
(While writing #391, I noticed...)
§3.13 makes repeated reference to capabilities "hav[ing] infinte bounds (see Section 2.1)", but the very short §2.1 does not define the term. Instead, that definition appears in §2.2.6, amidst the discussion of bounds encoding used in the draft.
And indeed, §2.2.6 itself seems a bit confused, referring the reader back to §2.1 for bounds decoding before launching into the details of bounds decoding. I suspect some historical editorial violence to the prose. ;)
I could suggest that there be a section introduced before §2.1 that gave a brief, abstract description of the components of capabilities, sort of like what the CHERI ISA documents have done, but that sounds like a fair bit of work for which I'm not champing at the bit to volunteer. As a simpler, hopefully sufficient, edit, could we just move the definition of "has infinite bounds" nearer the top of §2.2.6 and drop its erroneous xref to §2.1?