STIP CLIC implementation note for issue #222

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

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STIP CLIC implementation note for issue #222 #269

Closed dansmathers closed 2 years ago

dansmathers commented 2 years ago

For issue #222 Write a note with an example of how m-mode software can deliver timer interrupts to s-mode by setting clicintattr.trig to positive-edge-triggered.

Signed-off-by: Dan Smathers dan.smathers@seagate.com

dansmathers commented 2 years ago

note added manually to spec during TG meeting due to merge conflicts. closing this pull.