add csrrs mnxti behavior

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

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add csrrs mnxti behavior #344

Closed dansmathers closed 9 months ago

dansmathers commented 1 year ago

For issue #308, allows using CSRRS mnxti to compare valule in rs1 against clic.level instead of mcause.pil which could have been modified by pre-emption. (replaces pull #343)