adding Smstateen extension text to s-mode clic CSRs

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

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adding Smstateen extension text to s-mode clic CSRs #346

Closed dansmathers closed 1 year ago

dansmathers commented 1 year ago

For issue #345, add State enable text similar to that found in Zcmt spec for JVT CSR (although JVT CSR access causes an illegal instruction trap instead of ignoring writes and returning 0 on reads.