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riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
https://jira.riscv.org/browse/RVG-63
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Conflicting statements about switching from CLIC to CLINT #405

Closed Timmmm closed 1 day ago

Timmmm commented 1 week ago

When you switch from CLIC to CLINT mode the spec says:

The other new CLIC xcause fields, xpp and xpie, appear as zero in the xcause CSR but the corresponding state bits in the mstatus register are not cleared.

This doesn't make any sense because it also says:

The mcause.mpp and mcause.mpie fields typically mirror the mstatus.mpp and mstatus.mpie fields, and are aliased into mcause to reduce context save/restore code.

If they are aliased how do they have different values in xcause and xstatus?

Also typically is very imprecise.

christian-herber-nxp commented 1 week ago

Totally agree that the typical thing is to be fixed. The behavior in the first quote is the intended one.

jb-brelot-nxp commented 1 week ago

During the last clic meeting we discussed about this point. Thanks for opening this issue, We need to address it to make it clearer