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riscv / riscv-smmtt

This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
https://jira.riscv.org/browse/RVG-65
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Does the physical address generated by page table walk need to be checked by MTT？ #99

Closed jinyinghan324 closed 1 month ago

jinyinghan324 commented 1 month ago

In spec，it is said, " it simply provides access permissions for the physically addressed region/page (post any S-mode and/or G stage address translation) to enforce the isolation properties per the use case requirements".
I am confused about whether the physical address generated by page table walk need to be checked.

ved-rivos commented 1 month ago

I think the parenthetical should be removed. The MTT should be enforced on all implicit and explicit memory accesses when effective privilege mode of the access is less than M.

rsahita commented 1 month ago

This is in the non-normative section - fixing the description in an incoming PR with a reference to the normative section where the spec is clear in this aspect.

rsahita commented 1 month ago

@jinyinghan324 PTAL at PR #103

jinyinghan324 commented 1 month ago

Thank you