riscv / sail-riscv

Sail RISC-V model
https://lists.riscv.org/g/tech-golden-model
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Remove incorrect privilege assert #535

Closed PeterRugg closed 2 months ago

PeterRugg commented 2 months ago

The condition checks whether it's possible for a mode other than machine mode to take interrupts, but just because it can't, that doesn't mean we can never call this function while in another mode. In particular, this causes a crash if you run with S mode disabled but U mode enabled, then mret to U mode without NExt.

github-actions[bot] commented 2 months ago

Test Results

712 tests  ±0   712 :white_check_mark: ±0   0s :stopwatch: ±0s   6 suites ±0     0 :zzz: ±0    1 files   ±0     0 :x: ±0 

Results for commit 5fd15be9. ± Comparison against base commit a58c58c6.

:recycle: This comment has been updated with latest results.

Timmmm commented 2 months ago

Merging in a couple of days if nobody objects.