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riscv / sail-riscv

Sail RISC-V model
https://lists.riscv.org/g/tech-golden-model
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Zero mstatus.UPIE/UIE bits in legalize_mstatus #611

Closed Timmmm closed 3 weeks ago

Timmmm commented 3 weeks ago

This was missed when we removed the N extension.

I'm not really a fan of this code style - in other places we explicitly copy the bits that are implemented using their field names, which is also not ideal but definitely better and less error prone. We should change this code to do that at some point. I added a TODO.

github-actions[bot] commented 3 weeks ago

Test Results

396 tests  ±0   396 ✅ ±0   0s ⏱️ ±0s   4 suites ±0     0 💤 ±0    1 files   ±0     0 ❌ ±0 

Results for commit c75b379d. ± Comparison against base commit b8d1fa53.

Timmmm commented 3 weeks ago

Hmm I started it but it's a decently large refactoring which I don't really have time to do now, sorry. :-/

I think I'll just merge the fix and we can hopefully do it later.