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riscvarchive / riscv-v-spec

Working draft of the proposed RISC-V V vector extension
https://jira.riscv.org/browse/RVG-122
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vd's sign information in integer multiply-add instructions. #795

Open Zissi-Lei opened 2 years ago

Zissi-Lei commented 2 years ago

In integer multiply-add instructions, for expample, the vwmaccsu, only the sign information of vs1 and vs2 is given, but for vd I can't see it's sign information in spec. Is vd always treated as a signed number in all integer multiply-add instructions? Thanks for your time.

aswaterman commented 2 years ago

If either operand is signed, the result is signed. The spec doesn’t explicitly say so because this is implicitly true.

Zissi-Lei commented 2 years ago

If either operand is signed, the result is signed. The spec doesn’t explicitly say so because this is implicitly true.

Yes, but I mean that vd is also used as an operand. What's the signed information about vd as an operand?

nick-knight commented 2 years ago

The addition with vd is performed the same way whether you interpret the bits of vd as encoding a signed (two's complement) or unsigned integer. I think it makes more sense to think of vd (input and output) as a signed integer, but this interpretation doesn't change the semantics of the instruction.

aswaterman commented 2 years ago

For accumulating operations, the signedness of the accumulator doesn’t matter, because it’s just non-widening modular arithmetic (even when the product is widening).

aswaterman commented 2 years ago

But, conceptually, what Nick wrote matches how I think about these operations.