riscvarchive / riscv-v-spec

Working draft of the proposed RISC-V V vector extension
https://jira.riscv.org/browse/RVG-122
Creative Commons Attribution 4.0 International
973 stars 272 forks source link

Clarify that compares only AND in the mask if vd == v0 #901

Closed michael-platzer closed 1 year ago

michael-platzer commented 1 year ago

This PR clarifies that masked compares AND in the mask only if the destination register is v0, as discussed in #900

nick-knight commented 1 year ago

While we're here, I think "when mask-undisturbed" warrants a further clarification. Mask-producing instructions like these ignore vtype.vma and always have mask agnostic behavior. I think we should say something more explicit, like "on implementations that implement mask-agnostic as mask-undisturbed". Correctness of this example depends on implementation defined behavior, which is why I suggested removing it.

aswaterman commented 1 year ago

Is that really true? I know it’s the case for mask-logical instructions (which correspondingly aren’t allowed to be masked) but I don’t recall this being the case for comparisons.

nick-knight commented 1 year ago

My reading of https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#343-vector-tail-agnostic-and-vector-mask-agnostic-vta-and-vma is that inactive destination (mask) bits can be asserted.

aswaterman commented 1 year ago

What clause?

nick-knight commented 1 year ago

Paragraphs before and after the wall of \note{}s

aswaterman commented 1 year ago

Could you use some quotation marks? All I see that’s potentially relevant (but isn’t actually) is “Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of vta.”

nick-knight commented 1 year ago

A little further down:

When a set is marked agnostic, the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s. Within a single vector instruction, each destination element can be either left undisturbed or overwritten with 1s, in any combination, and the pattern of undisturbed or overwritten with 1s is not required to be deterministic when the instruction is executed with the same inputs.

Maybe I'm making a logical leap that I shouldn't?

aswaterman commented 1 year ago

What I am missing is what marks this particular set agnostic. I agree that writing 1 is legal for an agnostic mask bit, but what mandates the result of comparisons be agnostic?

michael-platzer commented 1 year ago

Mask-producing instructions like these ignore vtype.vma and always have mask agnostic behavior.

No. Mask-producing instructions are always tail agnostic but not mask agnostic.

nick-knight commented 1 year ago

Sorry. Please disregard my comments.