riscvarchive / riscv-v-spec

Working draft of the proposed RISC-V V vector extension
https://jira.riscv.org/browse/RVG-122
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benchmarks for RVV #914

Open wanghuibin0 opened 1 year ago

wanghuibin0 commented 1 year ago

I would like to evalute the V vector extension to compare it with other vector ISA, such as ARM SVE, or other SIMD architectures. Is there any representative benchmark for this task?

camel-cdr commented 1 year ago

@wanghuibin0 I don't think you'll be able to find something like that until rvv 1.0 CPUs are widely available.

This isn't quite what you are looking for, but I've created a few benchmarks to evaluate how to write performant rvv code: https://camel-cdr.github.io/rvv-bench-results/index.html

I've got results from the only two currently generally available CPUs with rvv support (C906 and C920), but note that they implement the pre ratification version 0.7.1 of the extension.

aitesam961 commented 1 year ago

Here is one but not quite there yet https://github.com/RALC88/riscv-vectorized-benchmark-suite and here is what they say "Current implementation is targeting RISC-V Architectures; however, it can be easily ported to any Vector/SIMD ISA thanks to a wrapper library which we developed to map vector intrinsics and math functions to the target architecture." Hope it helps