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riscvarchive / riscv-v-spec

Working draft of the proposed RISC-V V vector extension
https://jira.riscv.org/browse/RVG-122
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Signed averaging addition through vaadd #935

Open sun-jacobi opened 11 months ago

sun-jacobi commented 11 months ago

In 12.2, we introduce vaadd for averaging adds of signed integers.

The result would be rounded based on roundoff_signed function defined in 3.8. 

roundoff_signed(v, d) = (signed(v) >> d) + r

The r is based on the rounding mode (i.e. vxrm).

In most programming languages, signed averaging addition is attempting to round the result towards zero. AFAIU, This could not be achieved in each kind of rounding mode.

aswaterman commented 11 months ago

Yes, it's necessary to set vxrm to RDN to achieve this result. Since vxrm is caller-saved in the normal ABIs, it's usually cheap to change the rounding mode before a strip-mine loop that wants this behavior.

topperc commented 11 months ago

I think @sun-jacobi wants 0+-1 to give 0, but RDN would give -1. Using RUP with give 0, but would make 0+1 give 1.

aswaterman commented 11 months ago

Sorry, I was thinking about the unsigned variant. Yes, signed RTZ takes quite a few instructions to synthesize.