Closed theduke closed 3 years ago
Does RISC-V also use an UART compatible to the 16550 UART? In that case, I would be happy to merge a PR for RISC-V support.
Otherwise, this crate doesn't seem like the right place for such an implementation since the crate name indicates that it is specific to 16550-compatible UARTs. But I'm open to creating a general UART crate that supports multiple architectures and device types, if that's easily possible. I don't have time to work on it personally, but you're welcome to create a new project under the rust-osdev
organization if you want to implement something like that. Just let me know and I'll send you an invite.
Does RISC-V also use an UART compatible to the 16550 UART?
Sure, since UARTs are just IO devices many emalators (qemu et all) and some dev boards have (16550) UARTs.
RISC-V doesn't have custom io port instructions (in, out), the devices are just memory mapped.
Looking at the code, all that would really be needed for support is a cfg!
ed alternative implemenation of x86_64::instructions::port::Port
.
Maybe a platform-agnostic IoPort
trait would make sense.
Cool, I'd be happy to merge a PR for this then!
@theduke do you know what register width is used for MMIO access on RISC-V? Looking at the linux kernel documentation, it seems like the MMIO accesses can be either 1 byte, 2 byte, or 4 bytes.
Implemented in #15
Stumbled over this crate while writing a toy OS.
Currently only
x86
is supported (viax86_64::...::Port
).Would PR with RISC-V support be accepted?