securesystemslab / LLVM-MCA-Daemon

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Add `FetchDelay` stage #27

Closed andrej closed 2 weeks ago

andrej commented 2 weeks ago

This stage can be inserted between any other stages in the pipeline to introduce a latency penalty to instructions. The stage should behave transparently to the other stages except for the added cycle penalty. This means the stage will accept new instructions (isAvailable() == true) whenever the next stage is ready to accept new instructions. It will queue up these instructions and pass them to the next stage after holding them for a number of cycles. We will use this to add the branch misprediction latency later.