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sergeykhbr
/
riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
http://sergeykhbr.github.io/riscv_vhdl/
Apache License 2.0
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Should SRLW be I Type instead of R Type?
#48
dselke
closed
3 weeks ago
4
Any plans or suggestions for laticce or gowin fpga chips support?
#47
nerfur
closed
11 months ago
1
simulation of kc705_tb
#46
mito200
opened
1 year ago
19
Adding a Master peripheral
#45
Mina2411
opened
1 year ago
27
riscv_soc_tb Simulaton
#44
Youssef-IA
closed
1 year ago
18
Run Hello world example on VC707 board
#43
Mina2411
closed
1 year ago
24
slurm dependency
#42
ejessen
closed
1 year ago
3
How to generate VCD files of bare-metal dhrystone with _run_systemc_sim.sh?
#41
cnjsdfcy
closed
3 years ago
4
Build debugger with GUI failed: libdbg64g.so undefined reference
#40
HollaHieu
closed
3 years ago
1
Mesi
#39
himanshugupta30062
closed
2 years ago
0
GNSS module
#38
mfkiwl
closed
4 years ago
1
problem compilation with options: -march=rv64imafd -DFPU_ENABLED
#37
bitprog10
closed
2 years ago
1
can you run linux?
#36
rafaelcorsi
closed
2 years ago
2
Communicating with the ML605 Board (v8.0)
#35
gutkedu
closed
2 years ago
4
[!] Fix missing semicolon
#34
suzizecat
closed
4 years ago
0
gptimer alignment in the second timer is not correct
#33
hossameldin1995
closed
4 years ago
2
Error compiling debugger
#32
FrankAnze
closed
5 years ago
1
Uart Conf
#31
suhasskrishanmurthy
closed
4 years ago
1
Generating bit file for boot up using debugger
#30
taniyagarg4
closed
5 years ago
5
Openning ttyUSB0 at 115200 . . .failed"
#29
suhasskrishanmurthy
closed
4 years ago
3
showing CPU is turned off
#28
suhasskrishanmurthy
closed
5 years ago
1
Cannot find _run_functional_sim.sh
#27
suhasskrishanmurthy
closed
5 years ago
2
What configuration did you use for Rocket core?
#26
teadotjay
closed
5 years ago
2
Zynq-7000
#25
racarla
closed
5 years ago
2
freertos port for river core
#24
suhasskrishanmurthy
closed
5 years ago
3
Do you plan to write FPU for River CPU?
#23
hyf6661669
closed
5 years ago
1
Problems with building (or rather starting) the debugger
#22
nils1603
closed
5 years ago
1
fix #19
#21
mateoconlechuga
closed
6 years ago
1
Fix Vivado simulation
#20
mateoconlechuga
closed
6 years ago
0
Potential ICache Bug
#19
mateoconlechuga
closed
6 years ago
6
riscv_soc_tb crashes in Vivado Simulator
#18
mateoconlechuga
closed
6 years ago
2
loadelf is not working
#17
southlife
closed
6 years ago
4
Boot procedure bypass ROM FW copy to SRAM
#16
daffy1108
closed
6 years ago
3
A few questions
#15
mateoconlechuga
closed
6 years ago
5
How to build River CPU?
#14
mateoconlechuga
closed
6 years ago
3
MMU Support?
#13
mateoconlechuga
closed
6 years ago
2
missing packages?
#12
mattdaehn
closed
6 years ago
2
elf2raw64 и .shstrab
#11
kraziant
closed
6 years ago
6
[FIX]ed a warning via an explicit type conversion
#10
vepr-y
closed
6 years ago
1
how to generate bitstream file by myself ?
#9
gobs-code
closed
7 years ago
11
Generate failed of helloworld hex file
#8
gobs-code
closed
7 years ago
2
Will this fit on an Avnet S6microboard (Spartan6 LX9)
#7
salmansheikh
closed
7 years ago
1
compiling errors
#6
gobs-code
closed
7 years ago
2
Rtos port on RISC-V
#5
ninode
closed
7 years ago
3
The software models with GUI closes automatically
#4
satya123bora
closed
7 years ago
2
Check for failed invocations which would cause the debugger to crash.
#3
jrrk
closed
8 years ago
0
Building bootimage fails on linux using riscv-gcc 5.3.0
#2
bkoppelmann
closed
8 years ago
1
Bare-metal Rocket Chip
#1
pbn4
closed
8 years ago
1