sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
http://sergeykhbr.github.io/riscv_vhdl/
Apache License 2.0
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Rtos port on RISC-V #5

Closed ninode closed 7 years ago

ninode commented 7 years ago

Hello,

I'm doing an rtos port on RISC-V and currently working on the fpga-zynq/rocket-chip directory of Berkeley's.

Could you please provide instruction to how you used Vivado tools to generate another boot.bin which contains another os than linux with the rocket chip ? Did you use this directory at all ? What kind of files are necessary to have both the rocket cores and another os into the same boot.bin ?

Thank you very much

Regards

sergeykhbr commented 7 years ago

Hi,

I think you've a bit misunderstood the difference of projects for ZYNQ (ARM+FPGA) and pure FPGA projects. I do not use ZYNQ in my project and I do not use directory you've pointed to. So, I cannot help you to generate boot.bin file because I don't need to generate image for ARM at all.

Regards, Sergey

ninode commented 7 years ago

Hello,

Actually, is it possible to use your SoC FPGA Rocket sources and push them to a Zedboard to have Rocket cores on the FPGA fabric and not touch the ARM ?

Also, instead of Zephyr, is it possible to use my own sources for a ported RTOS in order to have: RTOS on ARM cores and Rocket cores on FPGA, without the boot.bin, but following your steps ?

Thank you

sergeykhbr commented 7 years ago

I am not experienced with ZYNQ but I see one common difference in FPGA startup process:

So, I suppose the answers on questions will be (my opinion only):

  1. It is possible to use Rocket sources on FPGA but ARM is always touched.
  2. You cannot load FPGA without boot.bin