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duh
👾 Design ∪ Hardware
https://observablehq.com/@drom/duh-intro
Apache License 2.0
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relax validation
#91
mrwinsto
opened
10 months ago
0
repetitive sets of items
#90
drom
opened
11 months ago
0
duh status command
#89
adeelliaquat-lm
opened
3 years ago
0
Install SuiteSparse header files during CI
#88
seldridge
closed
3 years ago
0
DuH validate not handling verbose port definitions
#87
seldridge
opened
3 years ago
0
DuH Validate Returns Zero Exit Code on Validation Failure
#86
seldridge
opened
3 years ago
1
Design option in "Block Type" doesn't create any (.json5) base document
#85
adeelliaquat-lm
opened
3 years ago
2
No module named 'cvxopt'
#83
davidmlw
closed
3 years ago
1
fixes #66
#82
Ramlakshmi3733
closed
3 years ago
0
duh validate doesn't work with absolute paths.
#81
rpadler
closed
3 years ago
3
Default value of access/modifiedWriteValue/readAction properties
#80
taichi-ishitani
closed
4 years ago
2
replace master/slave -> initiator/target
#79
drom
opened
4 years ago
1
duh validate should disallow duplicate address block names
#78
richardxia
closed
4 years ago
3
"component" is spelled wrong in validate command
#77
mwachs5
closed
4 years ago
0
think about linking programming interface to register description to bus interface
#76
drom
opened
4 years ago
0
detect type of the document
#75
drom
opened
4 years ago
0
component, busInterface, portMap, port concatenation
#74
drom
closed
4 years ago
0
warning about unmapped ports (component)
#73
drom
opened
4 years ago
0
duh validate issues a warning on bundles
#72
Ramlakshmi3733
closed
3 years ago
1
component -> busInterface -> port -> presence ('optional' by default)
#71
drom
closed
4 years ago
0
duh get the root document
#70
drom
closed
4 years ago
0
use duh-core
#69
drom
closed
4 years ago
0
report status of DUH document
#67
drom
opened
4 years ago
10
duh validate prints out unnecessary validation errors when DUH document not passed in
#66
richardxia
closed
3 years ago
2
https://duh.run website broken
#65
mithro
closed
4 years ago
3
Clarify README quickstart instructions regarding `duh` executable path
#64
richardxia
opened
4 years ago
0
cascading attributes: memoryMap -> register -> field
#63
drom
opened
4 years ago
0
Fetch $ref files
#62
drom
closed
4 years ago
0
duh validate returns 0 even if error is found
#60
jackkoenig
closed
4 years ago
0
duh validate doesn't find custom buses
#59
olofk
opened
4 years ago
2
inout verilog import - width missing
#58
drom
closed
3 years ago
4
CLIi to validate parameters against component parameter schema
#57
drom
opened
4 years ago
0
Create a Python library for working with DUH?
#56
mithro
opened
4 years ago
4
duh-design
#55
hiren-99
opened
5 years ago
0
import IP-XACT ports and SYSTEMRTL ports
#53
hiren-99
closed
5 years ago
1
Import memory map of verilog to json5.
#52
hiren-99
opened
5 years ago
0
duh-import-verilog-ports isuue
#51
hiren-99
closed
5 years ago
3
request for field to substitute different name for blackbox and block name
#50
ghost
opened
5 years ago
0
validate port interfaces mapped to existing ports
#49
drom
closed
5 years ago
0
Validate Bus Interfaces against Bus Definitions
#48
drom
closed
5 years ago
0
Duh import verilog ports issue
#47
v-krvavac
closed
5 years ago
3
Remove wake rules, they're out of date anyway
#46
jackkoenig
closed
5 years ago
0
Can't map parts of signals in duh
#40
v-krvavac
opened
5 years ago
0
Travis CI failing on Windows
#36
drom
opened
5 years ago
0
Travis CI failing on OSX
#35
drom
opened
5 years ago
0
Create LICENSE
#34
drom
closed
5 years ago
0
tick-define macro substituted with incorrect value in json5
#33
ghost
opened
5 years ago
1
verilog macro flagged as syntax error
#31
ghost
closed
5 years ago
5
pinlist empty if blank line after module module_name (
#30
ghost
closed
5 years ago
3
Issue in importing verilog ports to json5
#28
sidharth94
closed
5 years ago
2
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