FPGA Prototyping Error Caused by Vivado Tcl Interpreter: fpga-shells/xilinx/common/tcl/prologue.tcl

Background Work

[X] Yes, I searched the mailing list
[X] Yes, I searched prior issues
[X] Yes, I searched the documentation

Chipyard Version and Hash

Release: 1.5.0 Hash: a6a6a6

OS Setup

Distributor ID: Ubuntu Description: Ubuntu 20.04.3 LTS Release: 20.04 Codename: focal

Other Setup

Go through the standard FPGA prototyping flow in Chipyard Documentation

Current Behavior

As mentioned in Chipyard Google Group here:

When I excute the command "make SUB_PROJECT=vcu118 CONFIG=RocketVCU118Config bitstream" ERROR as follows:

source /home/liupeipei/chipyard/fpga/fpga-shells/xilinx/common/tcl/vivado.tcl
# set scriptdir [file dirname [info script]]
# source [file join $scriptdir "prologue.tcl"]
## set ip_vivado_tcls {}
## while {[llength $argv]} {
##   set argv [lassign $argv[set argv {}] flag]
##   switch -glob $flag {
##     -top-module {
##       set argv [lassign $argv[set argv {}] top]
##     }
##     -F {
##       # This should be a simple file format with one filepath per line
##       set argv [lassign $argv[set argv {}] vsrc_manifest]
##     }
##     -board {
##       set argv [lassign $argv[set argv {}] board]
##     }
##     -ip-vivado-tcls {
##       set argv [lassign $argv[set argv {}] ip_vivado_tcls]
##     }
##     -pre-impl-debug-tcl {
##       set argv [lassign $argv[set argv {}] pre_impl_debug_tcl]
##     }
##     -post-impl-debug-tcl {
##       set argv [lassign $argv[set argv {}] post_impl_debug_tcl]
##     }
##     -env-var-srcs {
##       set argv [lassign $argv[set argv {}] env_var_srcs]
##     }
##     default {
##       return -code error [list {unknown option} $flag]
##     }
##   }
## }
{unknown option} {}

    while executing
"source [file join $scriptdir "prologue.tcl"]"
    (file "/home/liupeipei/chipyard/fpga/fpga-shells/xilinx/common/tcl/vivado.tcl" line 7)
INFO: [Common 17-206] Exiting Vivado at Wed Mar  2 10:41:24 2022...
make: *** [Makefile:115: /home/liupeipei/chipyard/fpga/generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.RocketVCU118Config/obj/VCU118FPGATestHarness.bit] Error 1

Expected Behavior

The Tcl script should work fine with Error

Other Information

This is a bug of Vivado Tcl interpreter. I am not sure whether I should make a new pull request since the solution is a little bit dirty by modifying the file fpga/fpga-shells/xilinx/common/tcl/prologue.tcl. I provided the solution here in case someone else encounters this similar problem.

-ip-vivado-tcls {
  set ip_vivado_tcls {}
  while {[llength $argv]}  {
      set firstArg [lindex $argv 0]
      set isTclFile [string match *.tcl $firstArg]
      if {$isTclFile}         {
            puts "adding tcl file: ${firstArg}"
        set argv [lassign $argv[set argv {}] firstArg]
        lappend ip_vivado_tcls $firstArg
        puts "tcl file list: ${ip_vivado_tcls}"
      } else  {
          puts "terminate addition of tcl while argv= ${argv}"
          break
      }
  }
}

sifive / fpga-shells