wire out from dut.qspi(0).sck

[NaumanWazir]

Hi. I have to take a wire from dut.qspi(0).sck in ArtyShell.scala. I am trying to run e300 on Kintex. Since Kintex QSPI clock is only available through Startup2e. So I need to take wire from flash qspi clock and pass it to startup2e. In my opinion the good point to do that is ArtyShell line 176. I have tried but nothing is working. Can anybody tell how can I do it?

[mhanuel26]

Hi @NaumanWazir ,

Now I partially understand what freedom platform is doing with SPI clock asked here Now I am trying to use the startup2e instance since I am working on Arty S7, so far I haven't been abe to boot. What I did was to

1. Replace the IOBUF where you suggest

   //IOBUF(qspi_sck, dut.qspi(0).sck)
   val ip_qspi_sck = Module(new qspi_sck_bridge)
   qspi_sck := ip_qspi_sck.io.sck

2. Instantiate the startup2e IP, for this i have created a file called qspi_clk.v under fpgashells/xilinx/arty/vsrc with this content

module qspi_sck_bridge (
  output wire sck
);

STARTUPE2 #(
  .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
  .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
)
STARTUPE2_inst (
  .CFGCLK(open), // 1-bit output: Configuration main clock output
  .CFGMCLK(open), // 1-bit output: Configuration internal oscillator clock output
  .EOS(open), // 1-bit output: Active high output signal indicating the End Of Startup.
  .PREQ(open), // 1-bit output: PROGRAM request to fabric output
  .CLK(0), // 1-bit input: User start-up clock input
  .GSR(0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
  .GTS(0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
  .KEYCLEARB(0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
  .PACK(0), // 1-bit input: PROGRAM acknowledge input
  .USRCCLKO(sck), // 1-bit input: User CCLK input
  .USRCCLKTS(0), // 1-bit input: User CCLK 3-state enable input
  .USRDONEO(1), // 1-bit input: User DONE pin output control
  .USRDONETS(1) // 1-bit input: User DONE 3-state enable output
);
// End of STARTUPE2_inst instantiation

endmodule

`default_nettype wire

3. Add to Xilinx.scala

   
   //-------------------------------------------------------------------------
   // qspi_sck_bridge
   //-------------------------------------------------------------------------

class qspi_sck_bridge() extends BlackBox { val io = new Bundle{ val sck = Clock(OUTPUT) } }

4. Remove the qspi_clk constraint from xdc file 

5. Last but not least add the qspi_clk.v file to Makefile

$(FPGA_DIR)/$(BOARD)/vsrc/qspi_clk.v \

I have some problems with timing. I am not sure if FPGAChip.scala need to be modified, since direct clock is removed I commen the IOBUF line there too. 

Does someone from the freedom experts can see here what am I missing or doing wrong and please let me know?

I will appreciate your comments,