Quad 224 is where DRTIO CDR is happening, and the output from this quad may be more precise than after it has gone through more FPGA routing to reach quad 225 where MGT_CDR_CLK is currently connected.
OBUFDS_GTE3 may be even unable to obtain clocks from adjacent quads (see Figure 2-3 in ug576: I don't see a path from other quads).
I suggest swapping MGT_CDR_CLK and FCLKAC_N - Ethernet clocking will be fine with one quad crossed, and I have no use for the AMC fabric clock.
gkasprow
commented
5 years ago 
Quad 224 is where DRTIO CDR is happening, and the output from this quad may be more precise than after it has gone through more FPGA routing to reach quad 225 where MGT_CDR_CLK is currently connected. OBUFDS_GTE3 may be even unable to obtain clocks from adjacent quads (see Figure 2-3 in ug576: I don't see a path from other quads).
I suggest swapping MGT_CDR_CLK and FCLKAC_N - Ethernet clocking will be fine with one quad crossed, and I have no use for the AMC fabric clock.