[x] add test points to all power rails, slow busses (I2C/SPI) and other important signals. where possible also aim to expose all clocks via ufl or similar (e.g. if there is an unused output on a clock buffer then connect it to a UFL test point)
[x] for slow signals, don't make traces + vias unneccesarily small and don't cram components too close together (obviously, feel free to ignore this where it makes a genuine difference to SI/ease of layout, but don't just cram things together where they don't need to be)
[x] where possible (particularly slow signals) add 0R resistors that can be used to disconnect the signal and allow injection of an external signal. also consider adding 0R/DNP pull-ups/pull-downs on logic lines
[x] make sure that there is some accessible (e.g. by scratching off solder mask) ground/grounded test-points scattered on the top and bottom side
etc. Just standard good practice. This kind of thing makes debugging the EEMs much easier than debugging Sayma
added issue to make sure we don't forget about: