review

[gkasprow]

@filipswit I looked once again on the project and found a several mostly cosmetic issues:

• [x] use R10/R11/R28/R31 values to match other SInara board LED current (same brightness)
• [x] connect unused translator inputs to VCC or GND
• [x] If we lower R28 value, the logic level may be affected. I'm not sure about the T2 circuit anyway because LM75 has a low current capability. I'd add another FET and drive LD2B to GND.
• [x] I'd add pulldown resistor for OSC_EN_VADJ similar to R57, and R58. The default setting for IC1 should be an external clock because the internal one may be unknown before initiaisation.
• [x] choose resistor configuration for OSC1 in default variant (R3/R5)
• [x] remove R9 - it's overdriven by the translator anyway
• [x] make sure I2C devices do not conflict with
• [x] replace T200 with 2n700x to unify BOM?
• [x] IC204 has -1.21V annotation close to ADJ pin. Make sure it's 1/21 and change the sign
• [x] LT1963 will not be stable with C227. Replace it with a suitable tantalum one and make sure there are no bulk caps on this rail.
• [x] add P12V0/GND test points to the PSU board to enable soldering of supply cables during debugging.
• [x] the buck converter loop current is not optimal. Move the L200 up and output capacitors between IC100 and L200

[filipswit]

I'd add pulldown resistor for OSC_EN_VADJ similar to R57, and R58. The default setting for IC1 should be an external clock because the internal one may be unknown before initiaisation.

I've changed pd to pu on CLK_SEL_0, so now default input is (IN1) MMCX

LT1963 will not be stable with C227. Replace it with a suitable tantalum one and make sure there are no bulk caps on this rail.

Output caps C233 and C234 changed as well

add P12V0/GND test points to the PSU board to enable soldering of supply cables during debugging.

I've added also P3V3 test point and pu for power enable.

the buck converter loop current is not optimal. Move the L200 up and output capacitors between IC100 and L200

Now should be better: