Zotino v1.1

[hartytp]

• [x] Remove simulations page from schematic (let's just leave the Spice files in the repository)
• [x] Update power budget
• [x] Use two output resistors in series/parallel to improve power handling (200mW short-circuit)
• [x] reverse C143, C145, C147, C84
• [x] mirrored SOT23 diode footprint due to Altium bug - part of component is on top layer, pads are on bottom layer.
• [x] add Shottky diodes at the LDO outputs
• [x] 3mm higher EMC shield on PSU
• [ ] hole for heatsink in EMC shield
• [x] reverse IDC connector on BNC to IDC board
• [ ] Zero-index all channels
• [x] swap BNC connector GND terminals
• [x] either add ~2mm plastic washers on BNC barrel behind front panel or move BNC connectors 2mm towards FP. This is to enable fixing the BNC connectors to the panel using the screws.
• [x] Please remove the annotation "This module connects to Kasli ..." and replace it with something like "EEM connector: IO are LVDS, I2C is 3V3 LVCMOS, P3V3_MP up to 20mA, P12V up to 1A." (use same annotation as other EEMs)
• [x] run PI and thermal simulations. Please can you also double check that all regulators can handle the required current etc. Please also double check the layout for any places that could cause issues (bad cross-talk or patristics that could lead to oscillation, etc)
• ~Can we run the digital interface from 2V5?~ No -- see sampler discussions about this!
• [x] Fix temperature controller issues:
• [x] Silk + schematic + panel should be "v1.x" not "rev1.x" Silk should just say "Zotino v1.1" (copy from Sampler) still needs doing: Add Zotino name to schematic and pcb, add version number to schematic and front panel
• [x] Only have one set of +-12V regulators, not two!
• [x] Reduce SMPs outputs slightly, since we're only using +-12 regulators
• [x] Remove BNC to IDC connectors from this; they should be a separate project (they are a useful adapter for other boards like Sampler, and not part of the DAC design).
• [x] Upload BNC to IDC connector boards as a separate project.
• [x] Update front panel (see discussion in other issues)
• [x] Let's remove the simulations page from the schematic, better to just include the simulation itself in the project directory
• [x] Tidy up adapter boards cf comments here (two posts). Add annotations on silk and schematic for the adapter boards indicating how the connectors map to the channel (e.g. top=0, bottom=1 for the BNCs etc).
• [x] Remaining temperature controller issues here
• [x] Add more test points for power supply rails (both at the SMPS and for the LDOs), SPI, etc
• [x] For the TEC IDC, let's add a ground wire between the TEC and the thermistor to reduce EMI from the noisy TEC current (which is rectified by the temperature sensor, leading to errors).

[gkasprow]

@jordens these heat sinks have wrong fins direction. So won't work with air flow from bottom to top. These are typical 3U enclosures where board fits inside in the inner slot and the enclosure fits between 3U rails. It needs different panel. The hole distance is 85mm. I can't find this dimension in the datasheet. But once you mount it to the back of PCB, won't be able to fit into the rack.

[gkasprow]

@hartytp 15x15mm TEC, 2.5Ohm, 7W + 12.5mm heatsink fit perfectly

[gkasprow]

TEC model CP50441

[jordens]

Just fine for forced horizontal airflow. And AFAICT they will fit into the rack perfectly when the pcb is mounted to them. You only need a different front panel and card guide position.

[hartytp]

@gkasprow TEC and heat sink look good!

[gkasprow]

layout done, fixing some minor power integrity issues

[gkasprow]

Themal simulation with parameters - no air flow:

[gkasprow]

@hartytp DAC temp is 53 degrees without airflow When I specify it as -0.6W instead of +400mW, the temperature drops to 42.1 degrees. With airflow 20cm/s: temp is 31.7 with TEC cooling and airflow and 38.5 without TEC cooling and with airflow.

[gkasprow]

Temperature distribution with 20cm/s airflow

[gkasprow]

Current density for 12V rail. Far below limit.

And for -12V rail. After optimisation:

[a-shafir]

Can be improved:

1. C12.2 is connected so SIGGND but not AGND or ground plane.
2. J2.3 trace (and especially the via) looks weak
3. TEC1- pad clearance to SDO trace looks dangerous, can be short with hand soldering of TEC and burn the DAC.
4. Will TEC be powered from P3V3_MP? One pin of the signal cable IMHO it is not a good source for TEC power. Also it is shared power. Also it can be a long cable in some installations etc. Note: local P3V3 is also only 500mA max.

[a-shafir]

@gkasprow IMHO the TEC performance quickly degrades with the temperature drop. So will need more and more V*A to achieve the desired cold side temperature. Also it will heat the board around so with the temperature based feedback it is very difficult to stabilize. Do you have any estimation of the TEC current needed (worst case scenario)?

@hartytp i think need at least one more thermal sensor on board. Otherwise if we just trying to reach a target temperature in some cases for instance when the ambient is high it will lead to quite high power on TEC etc. The idea of @gkasprow "-0.6W instead of +400mW" will not work if we have only one sensor IMHO. I also not sure if a sensor on the regulator module can help. Basically we need to put one more sensor to the bottom-right side of the board and control it for a specific thermal difference between the sensors.

Also i think it still makes sense to add some thermal resistance for the ground plane. With V1.0 it was separated. Now it is tied. I think the optimal is somewhere in between.

[gkasprow]

@a-shafir Can be improved:

C12.2 is connected so SIGGND but not AGND or ground plane.

good catch, fixed

J2.3 trace (and especially the via) looks weak

OK, fixed, all current was passing via single pad

TEC1- pad clearance to SDO trace looks dangerous, can be short with hand soldering of TEC and burn the DAC.

there is solder mask, but I fixed

Will TEC be powered from P3V3_MP? One pin of the signal cable IMHO it is not a good source for TEC power. Also it is shared power. Also it can be a long cable in some installations etc. Note: local P3V3 is also only 500mA max.

nope, P3V3_MP is only to supply the I2C-> UART converter

[gkasprow]

@a-shafir in case of TEC I did experiments on prototype board. It needs very little power to cool by a few degrees. It has big heatsink above which has 10K/W at 200LFM (1m/s). We need max 1W of cooling power. Look at the plot below: Let's assume that the hot side is 50 degrees. We need max 10degrees of difference and max 1W of cooling power. This means that we need much less than 0.4A (approx 0.2A) at input voltage ~2V. That's why I did thermal simulation to see how much 1W of cooling power will change the DAC temperature. You are right - I simply placed negative power to the DAC instead of other side of the PCB. So I modified the design and attached thermal PAD to the TEC mode. Hyperlynx ignores components without pads. So at the moment I can model DAC power and TEC power. So with air flow of 1m/s at which TEC heatshink is specified, with -1W of Q, I get 20.5deg at the TEC pad and 23 deg at the DAC case. With Q=0 I get 26.5 at the TEC pad and 26.8 at the DAC. When I lower the air flow to 0.2m/s, the DAC temp is 45.7 and TEC pad temp is 45.1 With Q=1W the DAC temp is 39.4 deg. With Q=2W and 0.2m/s air flow we get: DAC temp = 33.3 deg This is the worst case scenario, with all components dissipating their max power. Remember one thing - the Peltier module to cool down by 10 degrees at Q=1W needs to have roughly 20deg of temp difference due to heatsik thermal resistance and 10 deg temp increase at 1W. So in our case with cold side at 30 deg and Q=1W we get heatsink temperature of 50 degrees.

[gkasprow]

The temperature sensor is placed as close as possible to the DAC case. It is also thermally connected with thermal pad using 6 vias. I cannot do much better. Where do you want to put another temperature sensor?

[gkasprow]

We would need to add to the heatsing to protect it against operation without the air flow. In such case the regulator will try to cool down the DAC but without proper ventilation, the hot side will get too hot and will destroy the TEC and possibly DAC because TEC will start heating instead of cooling. We can simply add thermal switch attached to the sink which will simply disconnect the TEC supply.

[hartytp]

@gkasprow Thanks for doing all that! Looks really good.

Thanks @a-shafir for the comments.

C12.2 is connected so SIGGND but not AGND or ground plane.

Yes, let's try to make sure that all of the various grounds around the DAC are tied as well as possible to a single solid ground plane.

With Q=0 I get 26.5 at the TEC pad and 26.8 at the DAC. When I lower the air flow to 0.2m/s, the DAC temp is 45.7 and TEC pad temp is 45.1 With Q=1W the DAC temp is 39.4 deg. With Q=2W and 0.2m/s air flow we get: DAC temp = 33.3 deg

That all sounds good @gkasprow.

Remember that the anticipated use case for Zotino is in a lab with decent temperature control, so the ambient temperature should only fluctuate by a degree or two (mainly due to variable power consumption of other EEMs in the same rack). So, we only want our TEC to change the DAC temperature by a couple of degrees max. The max TEC current should be up to +-1.5A (limited by the MaximIC peltier driver) so this gives us plenty of head room.

The fact that we have so much headroom suggests that (from a thermal perspective) we can afford to increase the amount of ground plane surrounding the DAC.

[hartytp]

Basically we need to put one more sensor to the bottom-right side of the board and control it for a specific thermal difference between the sensors.

I don't understand this point. We're aiming to control the DAC's absolute temperature, not its relative temperature.

One sensor should be fine.

Edit: a second sensor can be useful for diagnostics (e.g. to measure drifts in the temperature controller, but the IDC is already getting quite bit so I'm loathed to add another two pins to it for a diagnostic that we won't use very often).

[hartytp]

@gkasprow My feedback (other than the final issues above that remain outstanding):

• [x] Should we have a pin or two on the IDC to supply 12V power? My thinking here is that it would be nice for Thermostat be be able to operate in a mode where it's basically just a simple extension of Zotino, with power and I2C supplied via the cable.
• [x] Why is the heatsink "H6?" (why the question mark?)
• [x] If there is space to do it easily, shall we put test points on busy, LDAC, etc?
• [x] I haven't looked at the layout in detail, but obviously please do a final sanity check before manufacture. e.g. is all the grounding (particularly around the DAC/reference) as solid as possible. Has the routing been done to minimise cross-talk, etc.
• [x] What is C62 in terms of dielectric, voltage rating, etc? We should make sure this is a COG/NP0 with a decent voltage rating (in a decent size) to avoid excessive distortion. For components like this where the dielectric matters, please annotate that on the schematic (also applies to C61 and C56)
• [x] Should C129 be tantalum/have a tantalum in parallel with it (ensures that capacitance doesn't drop off due to the voltage and provides some damping to stop the LC ringing).
• [x] Add a note in the power budget that this does not include +-12V current consumed by the TEC driver, and that max current draw from that pin should be ?mA. Also add a "?mA max from +12V" annotation by the IDC connector on the schematic (replace ? with some sensible number).
• [x] In the power budget please can you give the +12V current draw as well as the power (this makes it easier for users to add up the current draw from the +12V rail for all of their EEMs to check it's below the max that can be supplied by Kasli).

[hartytp]

Other than that, I'm happy for this to go to manufacture as it is.

[hartytp]

We would need to add to the heatsing to protect it against operation without the air flow. In such case the regulator will try to cool down the DAC but without proper ventilation, the hot side will get too hot and will destroy the TEC and possibly DAC because TEC will start heating instead of cooling. We can simply add thermal switch attached to the sink which will simply disconnect the TEC supply.

@gkasprow We should be able to solve this in software on the temperature controller (Thermostat). e.g. one can set a max current and a shutoff temperature in the controller software. That should be sufficient to prevent damage without having to add extra thermal switches etc. Let's not overcomplicate the hardware for this.

[a-shafir]

@hartytp imagine we have the DAC not powered and rest of the board powered. So we will have let's say 28C the board temperature under the DAC. With the DAC powered it will be higher. So can compensate by the TEC the exceed heat from the DAC. In case if we will try to set the DAC 25C than there will be a temperature gradient so part of the board heat will be "pumped" with TEC. It looks like the ground plane thermal impedance us low. Greg can simulate how many W need to drop the temperature of the DAC few degree below the board temperature. And it is not impossible to have the board temperature 30-40C or even more in some hot places or with insufficient airflow. Any way, trying to drop the DAC temperature few deg under the surrounding PCB temperature will require high wattage of TEC and will make the situation even worst when the airflow is not good. So if we have 1 or 2 (diagonal across) the DAC sensors we can cool the DAC right to the board temperature with the low TEC wattage as @gkasprov planned.

In case if we need to cool it below the board temperature need to check the thermal impedance and the extra TEC power needed etc.

[gkasprow]

@a-shafir we can always set the temperature of the DAC a few degrees below the ambient. We don't care about absolute value but stability in long term. The conditions in the lab don't change that often.

[a-shafir]

@gkasprov yes, if we will follow the board temperature and if the airflow will be that high than will need around 1W. Than it makes sense to power the thermostat from 12V of course. But for this need more sensor(s) - see above message and also some more advanced thermostat logic or hw.

[gkasprow]

@a-shafir the regulator we will use supports only one sensor. We can add LM75 sensor on the board to sense ambient temperature. Then the regulator can be adjusted a few degrees below ambient.

[a-shafir]

@gkasprov You have the temp simulator. Can you try how many "minus W" need to apply for the DAC to make the current thermal sensor 5C below the board temperature few sm from the DAC?

[a-shafir]

@gkasprov what is the model of the regulator planned?

[gkasprow]

https://www.thorlabs.de/newgrouppage9.cfm?objectgroup_id=10626

[hartytp]

@a-shafir I'm not too worried about all of that.

Let's just stick with a single sensor rather than trying to overcomplicate all of this. Remember, the DAC doesn't have to be stabilised to mK, just to hundreds of mK in a rack that should be stable to a few K. Thus, we are only looking for a factor of 10 or so improvement in the ambient stability so we can ignore all second order effects.

[a-shafir]

@gkasprov my concern is not only temperature in the lab. If the airflow will not be sufficient the temperature inside of the case will slowly increase. Normally it finally (in hours) stabilizes because the efficiency of the cooling is increases with the device temperature (comparing to the ambient air). But in case of TEC if we are trying to hold a target temperature there is additional factor of the TEC hot side exceed power. So it is not impossible even a thermal runaway.

Also there are labs in hot places. Or what will happens if an unattended lab the air conditioning fails? If there is no target to keep the DAC at specific temperature indeed than there is certainly way to stay with low power on TEC using note sensors and also limit TEC power etc.

[gkasprow]

@a-shafir so we can add brutal switch mounted on the heatsink that will break the circuit.

[hartytp]

Currently, several of our designs will break without airflow (cf Kasli, unless the heatsink will fix that).

I'm not against a thermal switch if there is a really cheap, compact SMT option. But, I'm concerned that the complexity of this is the thing that's in most danger of going into runaway. We can always limit TEC V/I etc in software.

[a-shafir]

The protection is good to have.

Adding one more sensor cost nothing. In case of a programmable regulator it will allow to set the target temperature according to the situation.

You have all the data to decide.

[a-shafir]

"We can always limit TEC V/I etc in software."

Basically it even does not sounds crazy just to power TEC from a fixed wattage source! It will just do the job.

[hartytp]

Adding one more sensor cost nothing.

Well, you still have to pay someone to manually glue it to the heat sink and then wire it up to the PCB. Plus you have to sort out a comparator + thermal switch for the peltier. It all just seems like more hassle than it's worth IMHO.

Looking at Greg's simulations, the TEC power should be limited to about 1W by the TEC driver (which has user settable current and voltage limits for the Peltier). With a decent heatsink, that's not going to damage the TEC even if there isn't proper airflow (it's heatsunk to the PCB on one side and a heatsink on the other). So, I just don't see this ever leading to the TEC breaking so long as the temperature controller is configured properly.

[a-shafir]

Since we have a lot of options about the gateware having the heatsink on FPGA the must IMHO. As well as some thermal protection HW for the part that does not have it internally.

[hartytp]

I can't parse that sentence.

Look, let's keep this simple for the current version. If we have exploding TECs then we can add some extra protection.

In any case, how important is this? While we will probably want the TECs to get very good stability for Zotino, are other people (@jordens @dhslichter etc) also planning to use them? If this is something relatively niche that only we will use then I'm less concerned about making it indestructible.

[a-shafir]

"Well, you still have to pay someone to manually glue it to the heat sink and then wire it up to the PCB" for tracking the PCB temperature need a smd sensor on the PCB as I wrote initially. For TEC protection assuming we are not trying to lower the DAC temperature way below the PCB level.limiting the TEC power by 2w (for instance) shall be safe.

[hartytp]

What if we agree to just add a note on the schematic saying "2W max" by the IDC? Will that make everyone happy?

[a-shafir]

Note: "2W max" (and even 5W probably) will allow you to stabilize the DAC temperature assuming the rack temperature settled. But most likely it will be not enough to cool the DAC way below the board temperature because the major sources of hear around the DAC settled on the shared ground plane. So you still need yo know the board temperature to set the target for the regulator. So you need one more sensor on PCB. I2C sensor will work.

[hartytp]

Yes, one needs to know the ambient temperature, but one always needs to know that (it's generally not a good idea to pick a random temperature and rely of a lot of TEC power to reach it). However, that does not need a second sensor. The idea would be for the user to power the board with the TEC turned off, use the temperature controller (Thermistor) to measure the temperature and then use that as the set point.

Let's just leave the hardware as is and not bother with extra sensors.

[a-shafir]

Yep, with the i2c programmable TEC controller that allows to read the sensor it will work.

[jordens]

@gkasprow

• Does that heatsink-TEC stack fit into a 4HP slot?
• Is there no point in putting an LDO in front of the P3V3 to the DAC digital section? Isolation good enough in the DAC?
• Nor a choke on DVCC of the DAC to decouple it a bit from the other chips on that rail? Looks good otherwise!

@hartytp What stability and temperature coefficient do you expect with and without the TEC?

[gkasprow]

@jordens Yes, it fits in 4HP I already added LC filter at the DAC P3V3

[hartytp]

What stability and temperature coefficient do you expect with and without the TEC?

Target is <10ppm rms fluctuations (noise/drift) max over 24 hours (but ideally, more like a few ppm RMS) when used in a euro rack with few K fluctuations in temperature.

My memory of doing a detailed analysis of the stability of this board was that the stability is limited by the DAC (5ppm/K FSR typical)+ reference temp cos. Feeling was that it won't be quite good enough in a rack without some basic temperature control, but nothing particularly ambitious is needed.

Without the TEC, I'd expect something like 20ppm typical fluctuations with temperature (YMMV with conditions you mount the board in). With stabilisation, I expect few ppm stability easily (we've characterised a similar circuit based on these DACs before, and the stability was excellent once we added basic temperature stabilisation).

[jordens]

@hartytp In other words, temperature control gets you from 1 LSB stability to 0.1 LSB stability. I know where that's useful but the fact that quantization errors are now dominant by an order of magnitude definitely makes this a non-standard feature to me.

[hartytp]

@jordens yes. But, then so is the very low noise level that this board is targeting. It's also not that non-standard in the context of applying voltages to ion traps, where one often cares much more about stability than the exact value of the voltage.

Edit: in other words, I think the users are probably also non-standard (at least, the ones I've met are).

[hartytp]

@gkasprow did you manage to finish off the items at the top of this issue (can we close it)? In particular, did you zero-index the signals? The schematic can be done later if that helps, but it would be good to apply it to the silk + FP before manufacture?

[gkasprow]

In Altium you cannot count multi-channel designs from 0. So one bus is counted from 1, but all other things are zero-indexed. PCB marking is also 0-indexed. One can make Altum desing 0-indexed but then we would have to have 32 copies of the filter block on the schematic page

[gkasprow]

Yes, you can close it.