analog mezzanine physical/interface specification

[jordens]

Here is the final summary, based on comments in the thread below. This post will be sticky at the top, containing the most current specification. Items labeled ACTION: are not finalized yet; @dhslichter will edit this comment with the correct information as it is finalized.

Mezzanine geometry/stackup

• mezzanine board 32 x 100 mm, .047" nominal thickness, 4 layer boards
  • top and bottom layers to be Rogers 4350B, .020" thickness (cap construction for PCBs)
  • 50 ohm CPWG on .020" Rogers 4350B is .035" trace with .011" gaps
  • need ground stitch vias every ~.050" or less along both sides of CPWG
• mezzanines are mounted to RTM motherboard using 4x M1.5 screws
• 9 mm stand off between motherboard and mezzanine
• RF shields on both sides, separate cavities for each DAC channel and ADC channel (4 total per mezzanine)
  • interior height under DAC side shield lids needs to be .170" minimum (allowing for fabrication tolerances) to accommodate baluns
  • interior height under ADC side shield lids .120" (3 mm).

    Connectors

• power/IO: Samtec hermaphroditic, 40-pins connectors: LSS-120-01-L-DV-A and LSS-120-02-L-DV-A
• RF to/from motherboard
  • DACs: 4 SMP (2 differential pairs) - Molex 85305-0232
  • ADCs: 4 SMP (2 differential pairs) - SMP-MSLD-PCT-10
  • clock: 2 SMP (1 differential pair) generated on sayma_clk mezzanine - either style, depending on side of board where clock circuitry is needed.
• panel RF connection
  • see #7
  • option to have SMA shield isolated from Sayma ground (i.e. not grounded to panel) -- use plastic insulating washers on both sides of panel (e.g. http://www.rf-microwave.com/datasheets/603_Huber-Suhner_77-Z-0-0-8_01.pdf)
  • DAC side of board: 2 SMA (Telegartner J01151A0451)
  • ADC side of board: 2 SMA (Telegartner J01151A0921)
  • ACTION: use multi-coax assembly for front panel?

    Power rails

• +12VDC @ 200 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth
• +6VDC @ 1.5 A, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth
• -12VDC @ 50 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth
• -6VDC @ 150 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth
• no switching "spikes" on rails
• pi filters on all power lines
  • 0402 NP0 1 nF cap (16V min rating) parallel 0805 X7R 10 uF cap (16V min rating - Samsung CL21B106KOQNNN or equivalent DC bias performance -- degrades to 7.5 uF @ 3.3V, 5.5 uF @ 6V, 2.7 uF @ 12V) to ground, between mezzanine and choke
  • BLM41PG181SN1L choke
  • 0805 X7R 10 uF cap to ground (16V min rating - Samsung CL21B106KOQNNN or equivalent DC bias performance), between choke and supply
• desired supply voltages to be generated from these rails on mezzanine with dedicated LDOs
• no switching supplies on mezzanines
• +3.3VDC @ 1 A for digital-only devices on mezzanine. Should still be filtered on Sayma to minimize noise. max 10 mV p-p noise in 20 Hz-20 MHz bandwidth acceptable.
• single shared ground for analog and digital, connected to all SMP shields and all ground pins of power/IO connector

  Power/IO header routing

• as shown in image below from @gkasprow with exceptions listed below
• power line filters to pi filters as described above.
• digital lines IO0-IO15 3.3V LVCMOS
• I2C SDA/SCL (3.3V), pullup resistors to +3.3V installed on Sayma. I2C fed from I2C mux chips on Sayma card. Easy/compact level shifting on mezzanines (if needed) using discrete MOSFETs: http://www.nxp.com/documents/application_note/AN10441.pdf
• digital IO are general purpose in hardware, but for SPI preferred pinout is:
  • SCLK = IO0
  • MOSI = IO1
  • MISO = IO2
  • CS = IO3
  • additional chip selects starting with IO4 and up
• power rails as shown (7V rail is actually 6V)
• 4x connections to slow ADC (24-bit sigma-delta) for drift/temp/etc monitoring. ADC chip is mounted on See #11.

[gkasprow]

I did some estimation. We can easily fit four 32x100mm DAC/ADC mezzanines on RTM. We can even make them longer. On each of them we will fit four Wurth 30x30mm shields placed on both sides. In case of RF connectors I consider using: 2 high performance SMA, edge mount for DAC output 2 lower performance, right angled for ADC input. 8 SMP connectors for ADC/DAC. THT version with SMD central pad would give best mechanical properties. The distance between mezzanine and RTM is 9mm which is minimal value for SMP+bullet. For digital IO and control I'd like to use Samtec hermaphroditic, 40 pins connectors: LSS-120-01-L-DV-A and LSS-120-02-L-DV-A which combined give exactly 9mm. I use them in other projects and they work well with frequent mating. Mechanical mounting would be ensured by 4 x 2.6mm holes, 4 threaded spacers and 8 M2.5 screws. There is still place on front panel for SMA clock input I placed typical bulky SMA connectors to check the clearance between them. It is not that bad. Then are accessible with the wrench when the RTM is outside of the crate. Attached are PDF3D files with mezzanine and RTM. mezzanine.pdf RTM_DAC.pdf We will leave the space below mezzanines to enable the air flow. Some cut-outs in RTM may be necessary as well.

[gkasprow]

The clock module dimension is 43x80mm We can make it slightly longer when necessary here is the RTM with clock module RTM_DAC_clk.pdf

[jordens]

Thanks! Impressive.

• Is this still with the SMA firmly screwed into the front panel? How would the mezzanines mounted in that case?
• Did we want no common LO clock (for whatever upconversion needs there may be) to the mezzanines?
• I assume that there is still space for the dacs, adcs, power supplies, and clock fanout?

[sbourdeauducq]

I cannot open any of those PDFs, either with mupdf or Evince.

$ mupdf mezzanine.pdf 
error: expected trailer marker
error: cannot parse trailer
error: cannot read xref (ofs=617742)
error: cannot read xref at offset 617742

[whitequark]

@sbourdeauducq Yes. As far as I know PDF3D can be opened only with proprietary Adobe Reader for Linux.

[sbourdeauducq]

Adobe Reader freezes when trying to open those documents.

[sbourdeauducq]

Is there another format we can use for this?

[gkasprow]

we can use step

On 1 October 2016 at 18:10, Sébastien Bourdeauducq <notifications@github.com

wrote:

Is there another format we can use for this?

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/m-labs/sayma/issues/8#issuecomment-250920676, or mute the thread https://github.com/notifications/unsubscribe-auth/AEH-vmDbyZAy9Z5KatmKBP4HKPm_h3c3ks5qvoYFgaJpZM4KI9Wq .

[gkasprow]

To view step files I use free Design Spark Mechanic.

[whitequark]

FreeCAD is very bad but it should suffice to view STEP files.

[gkasprow]

Due to 10MB limit I had to zip them CLK module.zip mezzanine2.zip RTM_DAC_clk.zip

[gkasprow]

In case it pdf 3D files you have to use recent Adobe Acrobat Reder

[gkasprow]

Is this still with the SMA firmly screwed into the front panel? How would the mezzanines mounted in >that case?

the mezzanines are mounted to the RTM board using 4 M1.5 screws

Did we want no common LO clock (for whatever upconversion needs there may be) to the >mezzanines? I'll add another SMP connector I assume that there is still space for the dacs, adcs, power supplies, and clock fanout? sure, some of them can be plalced below the mezzanines

[gkasprow]

Is this still with the SMA firmly screwed into the front panel?

There are versions with long thread both right angle and straddle mounted. But their performance need to be verified since they are low cost. http://www.amphenolrf.com/132289.html http://www.rfstreet.com/ch_contentd.asp?id=2043 on the other side the assembly of the modules changed - they will be firmly attached to the rigid RTM board by 4 screws so it may be not necessary to screw them to the front panel

[sbourdeauducq]

Thanks. The STEP files work fine with FreeCAD. FYI, the Acrobat Android app and the Chrome PDF viewer also choke on the PDF3Ds.

[sbourdeauducq]

What is the idea behind having more SMPs than SMAs on the mezzanines? Since this also results in more SMPs than DAC/ADC channels on the RTM carrier, how will they be connected?

[gkasprow]

Did you enable the 3D view in AR?

It needs a while while opening the file

Greg

[gkasprow]

The signals of the ADCs and DACs are differential, that's why we need the SMPs doubled. The mezzanines inputs and outputs are single ended. The idea is to place baluns on the mezzanines because the way one feeds the ADC or couples to DAC depends on application.

[sbourdeauducq]

Aren't SMP connectors designed for single-ended unbalanced signals?

[gkasprow]

Well, in this way you can say that traces on PCB are designed for single ended signals. If you make differential traces that are loosely coupled, you can treat them as single ended. When you make traces tightly coupled, then they interfere with each other and if you split them then their impedance will increase. The same applies to SMAs - on every devkit you can connect gigabit transceivers using single-ended connectors. To transfer signals using SMPs you have to make impedance conversion from tightly coupled diff line to loosely coupled diff line and then transfer via connectors. So to make 100Ohm diff line you can use 2 traces wit 50Ohm but separated far away or use two 70Ohm traces coupled in such way that trace field see each other. In first case you can transfer them wia SMP, SMA or whatever, in second case you have to transfer the line to the first case.

On 2 October 2016 at 17:08, Sébastien Bourdeauducq <notifications@github.com

wrote:

Aren't SMPs designed for single-ended unbalanced signals?

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/m-labs/sayma/issues/8#issuecomment-250976000, or mute the thread https://github.com/notifications/unsubscribe-auth/AEH-vsgrE_lf4xOgCbkBVF6QfqKsdoFaks5qv8kIgaJpZM4KI9Wq .

[sbourdeauducq]

on every devkit you can connect gigabit transceivers using single-ended connectors.

Yes, but I've been suspicious of this and wondering if it were just a cheap hack. Is it actually working well?

[jordens]

This works perfectly fine. Convince yourself using the method of image charges and symmetries.

[dhslichter]

It's very hard to find true differential signal connectors where the channel-to-channel crosstalk is anywhere near as low as if one uses two coaxial connectors (e.g. SMP) for a differential signal. Sending the ADC/DAC differential signals over pairs of SMP connectors is the best compromise we could come up with given crosstalk/space/price/bandwidth/mating limitations and requirements.

[jbqubit]

Impressive drawings!

Wurth 30x30mm shields placed on both sides

• Should these also cover the back side where the SMP penetrate?
• A single shield on each side would give more freedom for component placement.
• What's the maximum vertical height for components? Is this sufficient for bulky components like baluns, transformers?

Is this still the plan?

• 4-layer PCB, top layer .020" Rogers 4350B
• single ground plane for analog and digital
  • Harty's comment: I tend to agree with the Good Book on EMC(http://www.amazon.com/Electromagnetic-Compatibility-Engineering-Henry-Ott/product-reviews/0470189304/ref=cm_cr_dp_see_all_btm?ie=UTF8&showViewpoints=1&sortBy=bySubmissionDateDescending) on this point that "thou shall have only one ground-plane before thee".
• separate power planes for analog and digital

[dhslichter]

Several points:

• if board will have components on both sides, should use Rogers 4350B on both sides. OK to make it thinner than .020" -- 50 ohm CPWG on .020" Rogers 4350B is 35 mil trace with 11 mil gaps, based on measurements at NIST.
• shields should be multi-cavity (if a single part) to reduce crosstalk between channels on the same daughtercard. Something along the lines of https://leadertechinc.com/product/multi-cavity-slot-lok/ would be good.
• interior height under shield lids needs to be .165" minimum to accommodate baluns
• crosstalk reduction would be improved if shields extend all the way to the end of the board, such that SMP connectors are connected through holes in the shields. Unshielded lengths should be short to the SMA connectors. Notches need to be made in the shields to avoid impedance discontinuities where CPWG traces exit from under the shields to the SMA connectors.

[gkasprow]

The Wurth shields were only placed just to reserve place on PCB. There are smaller ones like these http://www.digikey.com/product-search/en/rf-if-and-rfid/rf-shields/3539677?k=&pkeyword=&pv1217=1&FV=fff40036%2Cfff802dd%2C13040001%2C13040009&mnonly=0&newproducts=0&ColumnSort=0&page=1&quantity=0&ptm=0&fid=0&pageSize=25

[dhslichter]

Again, the shields you quote are not tall enough inside, nor would they extend the full size of the board. I understand the Wurth shields are placeholders, but I think we will probably want something custom/multicavity that covers as much of the board as possible while separating the various channels from each other.

[gkasprow]

In this case we can use custom Harwin shields (EZ-shield) where they can be freely adjusted with 5mm step. You just install clips on the PCB and then manually form the cover. http://www.mouser.com/new/harwin/harwin-ez-emi-rfi-shield-cans/

[jordens]

OK. @dhslichter and @gkasprow if you feel that you have arrived at a workable solution, please close the issue. AFAICT the rest has weighed in. And @sbouhabib. I'll assign it to @dhslichter once he has accepted.

[dhslichter]

@gkasprow can you clarify on which SMA connectors you want to use on the front panel, and their layout? Let's try to put the whole spec into a single comment at the end of the thread before we close.

[jbqubit]

Here's my summary of current design choices for mezzanine interface (and geometry) for each of 4 analog boards. @jordens @gkasprow @sbourdeauducq @dhslichter please review. @weidazh please forward to Harty

geometry and mechanical

• what is mezzanine geometry?
• the mezzanines are mounted to RTM motherboard using 4 of M1.5 screws

RF shield

• interior height under shield lids needs to be .165" minimum to accommodate baluns

PCB material/layers

• 4-layer PCB, top and bottom layers .020" Rogers 4350B
  • 50 ohm CPWG on .020" Rogers 4350B is 35 mil trace with 11 mil gaps
• single ground for analog and digital

connector choices

• power and IO
  • Samtec hermaphroditic, 40-pins connectors: LSS-120-01-L-DV-A and LSS-120-02-L-DV-A
  • 9 mm stand off between motherboard and mezzanine
  • what is maximum current?
• RF to/from motherboard
  • analog output: 4 SMP (2 differential pairs)
  • analog input: 4 SMP (2 differential pairs)
  • clock: 2 SMP (1 differential pair) generated on sayma_clk mezzanine
  • what is part number for SMP's? Discussed in #7 but not yet finalized?
• RF to outside world
  • SMA choice discussed in #7 but not yet finalized?

power/IO header routing

• digital
  • 18 digital lines total
  • no pull-up resistors
  • +3.3V LVCMOS single-ended to/from FPGA
  • recommended use:
  • pin names in schematic should include names indicative of recommended use case
  • I2C [I2C_SDA, I2C_SCL]
  • SPI [SPI_SCLK, SPI_MOSI, SPI_MISO, SPI_CS0, SPI_CS1, SPI_CS2, SPI_CS3, ...]
• analog power, low noise (generated on AMC)
  • +12V at 200 mA
  • -12V at 200 mA
  • +7V at 1 A
  • -7V at 1 A
  • +3.3V at 1 A
  • other potentials generated on-mezzanine using low-dropout regulators (LDR) -- no switching regulators on mezzanine
  • schematic notation to distinguish between analog and digital power
• digital power
  • +3.3 V at 1 A

ADCs

• 4 channels

[jbqubit]

@jordens Does github permit making an Issue comment as "sticky" so it rises to top? Seems like that's where the summary should lie.

[gkasprow]

During our last discussion we decided: +6V 1.5A. This minimizez LDO losses. We don't need -7 for RF stuff. +12V 200mA -12V 50mA no need for other power lines. I'd add local I2C line for module identification - the same mechanism as is on the FMCs. In this way we will quickly know which modules are installed in certain mezzanines. With all system enclosed in the rack it's good to know what is inserted in each RTM. To save pins, the I2C lines can be connected to the I2C muxes and later on to the Artix FPGA and in parallel to the IPMI link. To supply EEPROM and some digital stuff 3.3V is needed with low current capability. Now the connector looks like this;

[dhslichter]

Here is the final summary, based on comments from @gkasprow and @jbqubit in this thread. Items labeled ACTION: are not finalized yet; I will edit this comment with the correct information once they are finalized. @jordens @gkasprow @sbourdeauducq @jbqubit @weidazh please provide feedback.

Mezzanine geometry/stackup

• mezzanine board 32 x 100 mm, .062" nominal thickness, 4 layer boards
  • top and bottom layers to be Rogers 4350B, .020" thickness (cap construction for PCBs)
  • 50 ohm CPWG on .020" Rogers 4350B is .035" trace with .011" gaps
  • need ground stitch vias every ~.050" or less along both sides of CPWG
• mezzanines are mounted to RTM motherboard using 4x M1.5 screws
• 9 mm stand off between motherboard and mezzanine
• RF shields on both sides, separate cavities for each DAC channel and ADC channel (4 total per mezzanine)
  • interior height under shield lids needs to be .170" minimum (allowing for fabrication tolerances) to accommodate baluns

Connectors

• power/IO: Samtec hermaphroditic, 40-pins connectors: LSS-120-01-L-DV-A and LSS-120-02-L-DV-A
• RF to/from motherboard
  • DACs: 4 SMP (2 differential pairs) - Molex 85305-0232
  • ADCs: 4 SMP (2 differential pairs) - SMP-MSLD-PCT-10
  • clock: 2 SMP (1 differential pair) generated on sayma_clk mezzanine - either style, depending on side of board where clock circuitry is needed.
• panel RF connection
  • see #7
  • option to have SMA shield isolated from Sayma ground (i.e. not grounded to panel) -- use plastic insulating washers on both sides of panel (e.g. http://www.rf-microwave.com/datasheets/603_Huber-Suhner_77-Z-0-0-8_01.pdf)
  • DAC side of board: 2 SMA (Telegartner J01151A0451)
  • ADC side of board: 2 SMA (Telegartner J01151A0921)

Power rails

• +12VDC @ 200 mA, low noise
• +6VDC @ 1.5 A, low noise
• -12VDC @ 50 mA, low noise
• ACTION: need to specify noise requirement for above rails
• desired supply voltages to be generated from these rails on mezzanine with dedicated LDOs
• no switching supplies on mezzanines
• +3.3VDC @ 1 A for digital-only devices on mezzanine. Should still be filtered on Sayma to minimize noise.
• single shared ground for analog and digital, connected to all SMP shields and all ground pins of power/IO connector

Power/IO header routing

• as shown in image below from @gkasprow
• digital lines IO0-IO15 3.3V LVCMOS
• I2C SDA/SCL (3.3V), pullup resistors to +3.3V installed on Sayma. I2C fed from I2C mux chips on Sayma card. Easy/compact level shifting on mezzanines (if needed) using discrete MOSFETs: http://www.nxp.com/documents/application_note/AN10441.pdf
• digital IO are general purpose in hardware, but for SPI preferred pinout is:
  • SCLK = IO0
  • MOSI = IO1
  • MISO = IO2
  • CS = IO3
  • additional chip selects starting with IO4 and up
• power rails as shown (7V rail is actually 6V)
• 4x connections to slow ADC (24-bit sigma-delta) for drift/temp/etc monitoring. ADC chip is mounted on See #11.

[gkasprow]

I2C voltage is 3.3V. The calibration ADC is on the RTM board, controlled by Artix FPGA>

[gkasprow]

SMP part no is: MOLEX 85305-0232 for DAC signals Amphenol SMP-MSLD-PCT-10 for ADC signals With such scenario we will keep DAC signals on same layer and ADC signals on opposite layer. SMA part no is: Telegartner J01151A0451 for DAC signals. It is the only choice for desired performance. Telegartner J01151A0921 for ADC signals. This selection is forced by type of SMAs used for DACs. No other type of connector will fit.

[dhslichter]

There are still 4 unused pins on the power/IO header. Would it make sense to use these to make the ADC input lines into differential pairs? Thus there would be 8 pins total going to the slow ADC, which could be either used as 4 differential pairs or 8 single-ended lines with a chip like http://www.analog.com/en/products/analog-to-digital-converters/ad-converters/ad7173-8.html

[gkasprow]

I'd reserve them for future use. For sure we will find some application for them

On 11 October 2016 at 00:02, dhslichter notifications@github.com wrote:

There are still 4 unused pins on the power/IO header. Would it make sense to use these to make the ADC input lines into differential pairs? Thus there would be 8 pins total going to the slow ADC, which could be either used as 4 differential pairs or 8 single-ended lines with a chip like http://www.analog.com/en/products/analog-to-digital- converters/ad-converters/ad7173-8.html

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[dhslichter]

@gkasprow especially on the +12V and +6V rails, we need to make sure that the power line filter components are carefully chosen. 0201 package 1 nF capacitor will likely have very substantial DC bias dependence to capacitance (esp. if caps are only 16V rated, I would use larger margin for +12V rail), for example, and we should check choke impedance at 1.5A load for +6V rail.

[dhslichter]

Temperature monitoring can also be performed on mezzanines by using ADT7420, which contains conversion and I2C hardware, thus freeing slow ADC lines for e.g. monitoring of I/Q modulator drift or amplifier gain drift.

[gkasprow]

we can use 0402 NP0 instead

[gkasprow]

The chokes are rated for 3.5A BLM41PG181SN1L

On 11 October 2016 at 00:23, Grzegorz Kasprowicz < G.Kasprowicz@elka.pw.edu.pl> wrote:

we can use 0402 NP0 instead

[dhslichter]

I vote 0402 NP0 for the 1 nF, and X7R with higher voltage rating on the 10 uF if possible. Chokes look good.

[sbourdeauducq]

thus freeing slow ADC lines for e.g. monitoring of I/Q modulator drift or amplifier gain drift.

We also have an ADC inside the XC7A15T.

[jordens]

@jbqubit rises to the top of what? What you perceive as important might not be what is currently relevant to others. If you are certain this particular issue is more important than the other "important" issues, give it the aproriate label. You have lots of options to view issues in the way you prefer.

• make yourself a project dashboard where you can organize issues for yourself
• add labels and
• create permanent search links with special sorting to stuff with certain labels and
• bookmark them or add them to a wiki page or share them by other means.

@dhslichter looks good to me (apart from my usual concerns about layout density)

• Pi-filter (add caps after the chokes) so that the loads don't look into the high impedance chokes?
• I'd either keep editing the top post so that the status quo is immediately visible, or - if history is desired - edit a wiki page or text file in the repository for this, or split this into smaller issues.

[dhslichter]

@sbourdeauducq I am less concerned about the number of available ADC channels, was more thinking about the number of ADC signal lines coming out of the mezzanine (set at 4 right now). For a typical IQ modulator setup, we might be monitoring voltages (via lowpass filters) at the I port, Q port, RF port, and after the output amp, thus would use all the ADC lines in the I/O header for those and not have any for temp monitoring; the I2C temp monitor helps with that.

[dhslichter]

@jordens ack.

[dhslichter]

@gkasprow where will the SMP connectors providing a 100 MHz clock to the mezzanines go?

[gkasprow]

Do you mean RF_LO signal? The idea is to provide RF clock for up/down converters on the mezzanines. So I want to place SMP connectors routed to the clock module which may in the future provide such signal In case of the EXT_100M_RF_IN, it is routed directly to the SMA on RTM front panel.

[dhslichter]

I am thinking of a reference clock (e.g. 100 MHz) that will allow one to place a VCO/PLL on the mezzanine for generation of an LO to be mixed with the I/Q signals from the DACs to give an upconverted waveform. We had discussed the option of this architecture in addition to having the LO generated off-card and sent to the mezzanines via front-panel SMA.

So yes, one would want to have an SMP pair routed to the clock module from the Sayma board, or else via an SMA cable from the clock mezzanine. I believe Tom Harty had some notions on this laid out.