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sld-columbia / esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
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Unexpected error when building design containing 3 CPU cores #234

Open treble2 opened 3 months ago

treble2 commented 3 months ago

Describe the bug I run into the following error when building a design that has 3 CPU cores. I don't encounter this with designs that have 2 or 4 cores. image

To Reproduce Steps to reproduce the behavior:

  1. In the directory for the vc707 board, use the ESP GUI to configure a 2x3 array that instantiates 3 Ibex CPU cores, a MEM tile, and an I/O tile
  2. make vivado-syn

Expected behavior Successful build without errors

Desktop: