ProASIC3 port

[salmansheikh]

Hi Stephan,

I used your NEO some years back when developing a CAN Bus core. I loved it. I saw this under RISCV and decided to give it a try. I am porting it to the ProASIC3 starter board. I got it synthesized successfully in LiberoSOC v11.9. Just synplicity but it was bringing out all the wishbone signals. I tried to change the Booleans for the neorv32_top.vhd to the following (cut from file, not all of them) but I still see the signals on the RTL block diagram as I guess they are on the top level and need to be commented out of the entity definition and put in as signals in the body of the architecture. Otherwise lots of pins created and the compiler chokes on the signals not being driven.

-- External memory interface --
MEM_EXT_USE                  : boolean := false;  -- implement external memory bus interface?
IO_GPIO_USE                  : boolean := false;   -- implement general purpose input/output port unit (GPIO)?

Okay, I got it. I had to comment out all the wb and gpio signals from the entity, put them as signals in the architecture and then Simplicity optimized them away. Ran compile and now need to assign the 17 signals or so I have on the design out to pins and see if I can get it to run on the ProASIC3 board.

[salmansheikh]

The compiler tools are linux only. Do I need WSL or should I be able to find some pre-built windows executables?

[stnolting]

When you disable a certain optional module (like the GPIO unit) only the actual core logic gets discarded. Of course the top level ports are still there but there is no more logic driving/reading them.

I would suggest to use a wrapper instead of directly using neorv32_top.vhd as top entity. There are some wrappers available in https://github.com/stnolting/neorv32/tree/master/rtl/top_templates

For example, the neorv32_test_setup.vhd is a very simple wrapper only propagating the UART and GPIO ports to FPGA pins.

The compiler tools are linux only. Do I need WSL or should I be able to find some pre-built windows executables?

I have tried WSL and it is a bit unstable... I am using Ubuntu on Windows and that works pretty well.

There are pre-built toolchains for Windows out there. Maybe you could use the version from SiFive, but I haven't tried that yet.

[rcaproni]

Hi Guys:

About the compiler, I´m using windows only. I Installed the compiler from here: https://xpack.github.io/riscv-none-embed-gcc/install/ The version I´m using is 8.3.0-1.2.1 To compile using the makefile, you will need some modification:

• Install gcc riscv using XPACK
• Compile image_gen for windows (I used mingw64) and put in the image_gen folder
• Edit makefile

Compiler toolchain

XPACK_TOOLCHAIN ?= C:/Users/riscv/AppData/Roaming/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/8.3.0-1.2.1/.content RISCV_TOOLCHAIN ?= $(XPACK_TOOLCHAIN)/bin/riscv-none-embed

Disable image_gen compilation

$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.cpp

@echo Compiling $(IMAGE_GEN)

@$(CC_X86) $< -o $(IMAGE_GEN)

With these modifications you can use windows to compile and you will have the .bin file to upload to the board. I´ve been using it for months.

Regards Rodolfo

Em qui., 1 de out. de 2020 às 11:12, Stephan notifications@github.com escreveu:

When you disable a certain optional module (like the GPIO unit) only the actual core logic gets discarded. Of course the top level ports are still there but there is no more logic driving/reading them.

I would suggest to use a wrapper instead of directly using neorv32_top.vhd as top entity. There are some wrappers available in https://github.com/stnolting/neorv32/tree/master/rtl/top_templates

For example, the neorv32_test_setup.vhd https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd is a very simple wrapper only propagating the UART and GPIO ports to FPGA pins.

The compiler tools are linux only. Do I need WSL or should I be able to find some pre-built windows executables?

I have tried WSL and it is a bit unstable... I am using Ubuntu on Windows https://ubuntu.com/tutorials/ubuntu-on-windows#1-overview and that works pretty well.

There are pre-built toolchains for Windows out there. Maybe you could use the version from SiFive https://www.sifive.com/software, but I haven't tried that yet.

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub https://github.com/stnolting/neorv32/issues/1#issuecomment-702164145, or unsubscribe https://github.com/notifications/unsubscribe-auth/AJJNPLYMTR6BSXJDWH72WLDSISE6PANCNFSM4SAJPLBQ .

-- "Quis custodiet ipsos custodes?" ("Quem vigia os vigilantes?") Juvenal - Sátiras livro VI

[salmansheikh]

Yes, I a colleague reminded me of the SiFive stuff but I downloaded and my works symantec for some reason flagged all the files after I extracted them and added them to my windows path. I am trying the WSL route as I used it on my old laptop at work. I heard WSL 2 is better but in beta and looks to be a pain (for admins) to go through hoops to install.

I didn't look at the templates. I thought those were from the Lattice and Vivado only. I will use one of those next time. I got a simple design with just SPI and UART compiled and ready to program the Microsemi board. I may bring some GPIO for the LEDs before I do that.

Thanks.

[salmansheikh]

Hi Guys: About the compiler, I´m using windows only. I Installed the compiler from here: https://xpack.github.io/riscv-none-embed-gcc/install/ The version I´m using is 8.3.0-1.2.1 To compile using the makefile, you will need some modification: - Install gcc riscv using XPACK - Compile image_gen for windows (I used mingw64) and put in the image_gen folder - Edit makefile # Compiler toolchain XPACK_TOOLCHAIN ?= C:/Users/riscv/AppData/Roaming/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/8.3.0-1.2.1/.content RISCV_TOOLCHAIN ?= $(XPACK_TOOLCHAIN)/bin/riscv-none-embed Disable image_gen compilation #$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.cpp # @echo Compiling $(IMAGE_GEN) # @$(CC_X86) $< -o $(IMAGE_GEN) With these modifications you can use windows to compile and you will have the .bin file to upload to the board. I´ve been using it for months. Regards Rodolfo Em qui., 1 de out. de 2020 às 11:12, Stephan notifications@github.com escreveu: … When you disable a certain optional module (like the GPIO unit) only the actual core logic gets discarded. Of course the top level ports are still there but there is no more logic driving/reading them. I would suggest to use a wrapper instead of directly using neorv32_top.vhd as top entity. There are some wrappers available in https://github.com/stnolting/neorv32/tree/master/rtl/top_templates For example, the neorv32_test_setup.vhd https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd is a very simple wrapper only propagating the UART and GPIO ports to FPGA pins. The compiler tools are linux only. Do I need WSL or should I be able to find some pre-built windows executables? I have tried WSL and it is a bit unstable... I am using Ubuntu on Windows https://ubuntu.com/tutorials/ubuntu-on-windows#1-overview and that works pretty well. There are pre-built toolchains for Windows out there. Maybe you could use the version from SiFive https://www.sifive.com/software, but I haven't tried that yet. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#1 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AJJNPLYMTR6BSXJDWH72WLDSISE6PANCNFSM4SAJPLBQ . -- "Quis custodiet ipsos custodes?" ("Quem vigia os vigilantes?") Juvenal - Sátiras livro VI

Thanks but I am using a work computer and don't have elevated privileges so I may go with WSL for now. This is more involved. On my home machine, I can do these easily .Heck my home machine is an Ubuntu. No windows here..

[salmansheikh]

I didn't have gcc or g++ installed. I thought they would be installed by default. now the toolchain works and I can build examples. Onwards!!!

[stnolting]

@rcaproni Nice solution for Windows! I did not know https://xpack.github.io/riscv-none-embed-gcc/install/. I definitively have to try that out.

[rcaproni]

@rcaproni Nice solution for Windows! I did not know https://xpack.github.io/riscv-none-embed-gcc/install/. I definitively have to try that out.

Yes, good solution provided by mcu-eclipse guys. Works fine for NEORV.