sy2002
commented
4 years ago As decided in our videochat, here is the way forward:
About Overflow
Change overflow handling to "correct behaviour", which is: Is written in the comment of the emulator and what is written here:
http://www.righto.com/2012/12/the-6502-overflow-flag-explained.html
Branch subroutine calls should not modify the status register (just as the hardware is doing right now in V1.6)
About Compare
Change compare to implement a SUB instruction without writing back the results.
CAUTION: THESE CHANGES WILL BREAK ALL EXISTING SOFTWARE IN SUBTLE AND NOT SO SUBTLE WAYS - A LOT OF DEBUGGING REQUIRED
There are open questions that came up while Michael created the great and comprehensive new
test_programs/cpu_test.asm. Some of them are described here: https://github.com/sy2002/QNICE-FPGA/issues/53#issuecomment-673674143 and some of them are described here: https://github.com/sy2002/QNICE-FPGA/issues/50, https://github.com/sy2002/QNICE-FPGA/issues/40 and https://github.com/sy2002/QNICE-FPGA/issues/37The compromise solution for now is: On the emulator, Bernd already implemented the "non forgetting" SR register and we should also change the hardware accordingly, because this does not seem to break things: https://github.com/sy2002/QNICE-FPGA/issues/53#issuecomment-673674143
Still open are topics around the
Vflag, CMP semantics and other topics.So this issue is about
Vflag which is today simply implented as: "adding/subtracting two positive numbers and getting a negative result or adding/subtracting two negative numbers and getting a positive result"As for the time of creating this issue, we already foresee, that the following might turn out into a large undertaking. So it is labled with "V1.7" as a placeholder for "not in V1.6 but later"